| Message ID | 20220522162802.208275-12-luca@z3ntu.xyz |
|---|---|
| State | New |
| Headers | show |
| Series | CAMSS support for MSM8974 | expand |
This patch does not apply on upstream-media/master or upstream-next/master. Is there another branch this series should be applied to? On Sun, 22 May 2022 at 18:28, Luca Weiss <luca@z3ntu.xyz> wrote: > > Add a node for the camera-specific i2c bus found on msm8974. > > Signed-off-by: Luca Weiss <luca@z3ntu.xyz> > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 62 +++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > index ffa6f874917a..a80b4ae71745 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -1434,6 +1434,34 @@ blsp2_i2c5_sleep: blsp2-i2c5-sleep { > > /* BLSP2_I2C6 info is missing - nobody uses it though? */ > > + cci0_default: cci0-default { > + pins = "gpio19", "gpio20"; > + function = "cci_i2c0"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cci0_sleep: cci0-sleep { > + pins = "gpio19", "gpio20"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cci1_default: cci1-default { > + pins = "gpio21", "gpio22"; > + function = "cci_i2c1"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cci1_sleep: cci1-sleep { > + pins = "gpio21", "gpio22"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > spi8_default: spi8_default { > mosi { > pins = "gpio45"; > @@ -1587,6 +1615,40 @@ dsi0_phy: dsi-phy@fd922a00 { > }; > }; > > + cci: cci@fda0c000 { > + compatible = "qcom,msm8974-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xfda0c000 0x1000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; > + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, > + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, > + <&mmcc CAMSS_CCI_CCI_CLK>; > + clock-names = "camss_top_ahb", > + "cci_ahb", > + "cci"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-1 = <&cci0_sleep &cci1_sleep>; > + > + status = "disabled"; > + > + cci_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <400000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > gpu: adreno@fdb00000 { > compatible = "qcom,adreno-330.1", "qcom,adreno"; > reg = <0xfdb00000 0x10000>; > -- > 2.36.0 >
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ffa6f874917a..a80b4ae71745 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1434,6 +1434,34 @@ blsp2_i2c5_sleep: blsp2-i2c5-sleep { /* BLSP2_I2C6 info is missing - nobody uses it though? */ + cci0_default: cci0-default { + pins = "gpio19", "gpio20"; + function = "cci_i2c0"; + drive-strength = <2>; + bias-disable; + }; + + cci0_sleep: cci0-sleep { + pins = "gpio19", "gpio20"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default { + pins = "gpio21", "gpio22"; + function = "cci_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + cci1_sleep: cci1-sleep { + pins = "gpio21", "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + spi8_default: spi8_default { mosi { pins = "gpio45"; @@ -1587,6 +1615,40 @@ dsi0_phy: dsi-phy@fd922a00 { }; }; + cci: cci@fda0c000 { + compatible = "qcom,msm8974-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfda0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: adreno@fdb00000 { compatible = "qcom,adreno-330.1", "qcom,adreno"; reg = <0xfdb00000 0x10000>;
Add a node for the camera-specific i2c bus found on msm8974. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> --- arch/arm/boot/dts/qcom-msm8974.dtsi | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+)