| Message ID | 20220520154051.29088-2-phil.edworthy@renesas.com |
|---|---|
| State | Accepted |
| Commit | 34e3b69b1edc966f0f4dcdd880afba3a2dad8c09 |
| Headers | show |
| Series | [1/2] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/V2M pinctrl | expand |
On Fri, 20 May 2022 16:40:50 +0100, Phil Edworthy wrote: > Add device tree binding documentation and header file for Renesas > RZ/V2M pinctrl. > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../pinctrl/renesas,rzv2m-pinctrl.yaml | 174 ++++++++++++++++++ > include/dt-bindings/pinctrl/rzv2m-pinctrl.h | 23 +++ > 2 files changed, 197 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/rzv2m-pinctrl.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.example.dts:22:18: fatal error: dt-bindings/clock/r9a09g011-cpg.h: No such file or directory 22 | #include <dt-bindings/clock/r9a09g011-cpg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hi Rob Thanks for the review! On 24 May 2022 19:47 Rob Herring wrote: > On Fri, May 20, 2022 at 04:40:50PM +0100, Phil Edworthy wrote: > > Add device tree binding documentation and header file for Renesas > > RZ/V2M pinctrl. > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > .../pinctrl/renesas,rzv2m-pinctrl.yaml | 174 ++++++++++++++++++ > > include/dt-bindings/pinctrl/rzv2m-pinctrl.h | 23 +++ > > 2 files changed, 197 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > > create mode 100644 include/dt-bindings/pinctrl/rzv2m-pinctrl.h > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m- > pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m- > pinctrl.yaml > > new file mode 100644 > > index 000000000000..305e836cf0a3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m- > pinctrl.yaml > > @@ -0,0 +1,174 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml# > > +$schema: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml# > > + > > +title: Renesas RZ/V2M combined Pin and GPIO controller > > + > > +maintainers: > > + - Geert Uytterhoeven <geert+renesas@glider.be> > > + - Phil Edworthy <phil.edworthy@renesas.com> > > + > > +description: > > + The Renesas RZ/V2M SoC features a combined Pin and GPIO controller. > > + Pin multiplexing and GPIO configuration is performed on a per-pin > basis. > > + Each port features up to 16 pins, each of them configurable for GPIO > function > > + (port mode) or in alternate function mode. > > + Up to 8 different alternate function modes exist for each single pin. > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - const: renesas,r9a09g011-pinctrl # RZ/V2M > > With only 1, you can drop 'oneOf' and 'items'. Will do! > > + > > + reg: > > + maxItems: 1 > > + > > + gpio-controller: true > > + > > + '#gpio-cells': > > + const: 2 > > + description: > > + The first cell contains the global GPIO port index, constructed > using the > > + RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m- > pinctrl.h> and the > > + second cell represents consumer flag as mentioned in > ../gpio/gpio.txt > > + E.g. "RZV2M_GPIO(8, 1)" for P8_1. > > + > > + gpio-ranges: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 39 > > Needs some description as to what all these are. If it is not all the > same kind of interrupt, then each one has to be listed. Ok, I'll see what is best to describe these. Thanks Phil
Hi Phil, On Fri, May 20, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote: > Add device tree binding documentation and header file for Renesas > RZ/V2M pinctrl. > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml > @@ -0,0 +1,174 @@ > +additionalProperties: > + anyOf: > + - type: object > + allOf: > + - $ref: pincfg-node.yaml# > + - $ref: pinmux-node.yaml# > + > + description: > + Pin controller client devices use pin configuration subnodes (children > + and grandchildren) for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + phandle: true > + pinmux: > + description: > + Values are constructed from GPIO port number, pin number, and > + alternate function configuration number using the RZV2M_PORT_PINMUX() > + helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>. > + pins: true > + bias-disable: true > + bias-pull-down: true > + bias-pull-up: true > + drive-strength-microamp: > + # Superset of supported values > + enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000, > + 9000, 9600, 11000, 12000, 13000, 18000 ] > + > + power-source: > + description: I/O voltage in millivolt. > + enum: [ 1800, 3300 ] Is power-source actually supported? While the documentation shows there are some 1.8/3.3V pin groups, I didn't find how to switch voltage? > + slew-rate: true What are valid values? Looking at the code, 0 = slow, 1 = fast? > + gpio-hog: true > + gpios: true > + input-enable: true Missing output-enable? > + output-high: true > + output-low: true > + line-name: true Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for your review! On 14 June 2022 13:10 Geert Uytterhoeven wrote: > On Fri, May 20, 2022 at 5:41 PM Phil Edworthy wrote: > > Add device tree binding documentation and header file for Renesas > > RZ/V2M pinctrl. > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m- > pinctrl.yaml > > @@ -0,0 +1,174 @@ > > > +additionalProperties: > > + anyOf: > > + - type: object > > + allOf: > > + - $ref: pincfg-node.yaml# > > + - $ref: pinmux-node.yaml# > > + > > + description: > > + Pin controller client devices use pin configuration subnodes > (children > > + and grandchildren) for desired pin configuration. > > + Client device subnodes use below standard properties. > > + > > + properties: > > + phandle: true > > + pinmux: > > + description: > > + Values are constructed from GPIO port number, pin number, > and > > + alternate function configuration number using the > RZV2M_PORT_PINMUX() > > + helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>. > > + pins: true > > + bias-disable: true > > + bias-pull-down: true > > + bias-pull-up: true > > + drive-strength-microamp: > > + # Superset of supported values > > + enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000, > > + 9000, 9600, 11000, 12000, 13000, 18000 ] > > + > > + power-source: > > + description: I/O voltage in millivolt. > > + enum: [ 1800, 3300 ] > > Is power-source actually supported? > While the documentation shows there are some 1.8/3.3V pin groups, > I didn't find how to switch voltage? You are right, there is no way to change the voltage, the I/O voltage is based on Vdd pin input voltages. See PAMODVDD, PBMODVDD, PCMODVDD, SD0MODVDD, SD1MODVDD, etc pins. > > + slew-rate: true > > What are valid values? > Looking at the code, 0 = slow, 1 = fast? Good point, I'll add enum: [0, 1] and a description. > > + gpio-hog: true > > + gpios: true > > + input-enable: true > > Missing output-enable? If it's an output, wouldn't you only want to set it high or low? > > + output-high: true > > + output-low: true > > + line-name: true Thanks Phil
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml new file mode 100644 index 000000000000..305e836cf0a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M combined Pin and GPIO controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Phil Edworthy <phil.edworthy@renesas.com> + +description: + The Renesas RZ/V2M SoC features a combined Pin and GPIO controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 16 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - items: + - const: renesas,r9a09g011-pinctrl # RZ/V2M + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the + second cell represents consumer flag as mentioned in ../gpio/gpio.txt + E.g. "RZV2M_GPIO(8, 1)" for P8_1. + + gpio-ranges: + maxItems: 1 + + interrupts: + maxItems: 39 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + pinmux: + description: + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZV2M_PORT_PINMUX() + helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>. + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength-microamp: + # Superset of supported values + enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000, + 9000, 9600, 11000, 12000, 13000, 18000 ] + + power-source: + description: I/O voltage in millivolt. + enum: [ 1800, 3300 ] + slew-rate: true + gpio-hog: true + gpios: true + input-enable: true + output-high: true + output-low: true + line-name: true + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupts + - clocks + - power-domains + - resets + +examples: + - | + #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl: pinctrl@b6250000 { + compatible = "renesas,r9a09g011-pinctrl"; + reg = <0xb6250000 0x800>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 352>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; + resets = <&cpg R9A09G011_PFC_PRESETN>; + power-domains = <&cpg>; + + i2c2_pins: i2c2 { + pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */ + <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */ + }; + }; diff --git a/include/dt-bindings/pinctrl/rzv2m-pinctrl.h b/include/dt-bindings/pinctrl/rzv2m-pinctrl.h new file mode 100644 index 000000000000..525532cd15da --- /dev/null +++ b/include/dt-bindings/pinctrl/rzv2m-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/V2M pinctrl bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZV2M_PINCTRL_H +#define __DT_BINDINGS_RZV2M_PINCTRL_H + +#define RZV2M_PINS_PER_PORT 16 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */