diff mbox series

[v7,3/6] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks

Message ID 20220520015844.1190511-4-dmitry.baryshkov@linaro.org
State New
Headers show
Series PCI: qcom: Rework pipe_clk/pipe_clk_src handling | expand

Commit Message

Dmitry Baryshkov May 20, 2022, 1:58 a.m. UTC 
Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-sm8450.c | 72 +++++++++++------------------------
 1 file changed, 22 insertions(+), 50 deletions(-)

Comments

Dmitry Baryshkov May 20, 2022, 4:54 p.m. UTC | #1 
On Fri, 20 May 2022 at 19:09, Johan Hovold <johan@kernel.org> wrote:
>
> On Fri, May 20, 2022 at 04:58:41AM +0300, Dmitry Baryshkov wrote:
> > Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
> > the clock framework automatically park the clock when the clock is
> > switched off and restore the parent when the clock is switched on.
> >
> > Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> For the benefit of others using the new phy_mux implementation, it would
> have been better to just do a revert of the safe-mux change. Would make
> reviewing easier too.

Fine with me, I hesitated between these two variants and settled on
having a smaller amount of noise. I'll change this in next iteration.

>
> > ---
> >  drivers/clk/qcom/gcc-sm8450.c | 72 +++++++++++------------------------
> >  1 file changed, 22 insertions(+), 50 deletions(-)
>
> > -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> > -     .reg = 0x7b060,
> > -     .shift = 0,
> > -     .width = 2,
> > -     .safe_src_parent = P_BI_TCXO,
> > -     .parent_map = gcc_parent_map_4,
> > -     .clkr = {
> > -             .hw.init = &(struct clk_init_data){
> > -                     .name = "gcc_pcie_0_pipe_clk_src",
> > -                     .parent_data = gcc_parent_data_4,
> > -                     .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> > -                     .ops = &clk_regmap_mux_safe_ops,
> > +static struct clk_regmap gcc_pcie_0_pipe_clk_src = {
> > +     .enable_reg = 0x7b060,
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "gcc_pcie_0_pipe_clk_src",
> > +             .parent_data = &(const struct clk_parent_data){
> > +                     .fw_name = "pcie_0_pipe_clk",
> >               },
> > +             .num_parents = 1,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +             .ops = &clk_regmap_phy_mux_ops,
> >       },
> >  };
>
> And again, this would be easier to understand with a dedicated struct
> clk_regmap_phy_mux (whose definition you can look up and find a
> description of how it is intended to be use).

Or one can lookup the definition of clk_regmap_phy_mux_ops and read
the corresponding text. But I see your point, let's bring it back.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index fb6decd3df49..8a62f141ab23 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -26,9 +26,7 @@  enum {
 	P_GCC_GPLL0_OUT_MAIN,
 	P_GCC_GPLL4_OUT_MAIN,
 	P_GCC_GPLL9_OUT_MAIN,
-	P_PCIE_0_PIPE_CLK,
 	P_PCIE_1_PHY_AUX_CLK,
-	P_PCIE_1_PIPE_CLK,
 	P_SLEEP_CLK,
 	P_UFS_PHY_RX_SYMBOL_0_CLK,
 	P_UFS_PHY_RX_SYMBOL_1_CLK,
@@ -153,16 +151,6 @@  static const struct clk_parent_data gcc_parent_data_3[] = {
 	{ .fw_name = "bi_tcxo" },
 };
 
-static const struct parent_map gcc_parent_map_4[] = {
-	{ P_PCIE_0_PIPE_CLK, 0 },
-	{ P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_4[] = {
-	{ .fw_name = "pcie_0_pipe_clk", },
-	{ .fw_name = "bi_tcxo", },
-};
-
 static const struct parent_map gcc_parent_map_5[] = {
 	{ P_PCIE_1_PHY_AUX_CLK, 0 },
 	{ P_BI_TCXO, 2 },
@@ -173,16 +161,6 @@  static const struct clk_parent_data gcc_parent_data_5[] = {
 	{ .fw_name = "bi_tcxo" },
 };
 
-static const struct parent_map gcc_parent_map_6[] = {
-	{ P_PCIE_1_PIPE_CLK, 0 },
-	{ P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_6[] = {
-	{ .fw_name = "pcie_1_pipe_clk" },
-	{ .fw_name = "bi_tcxo" },
-};
-
 static const struct parent_map gcc_parent_map_7[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -239,19 +217,16 @@  static const struct clk_parent_data gcc_parent_data_11[] = {
 	{ .fw_name = "bi_tcxo" },
 };
 
-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
-	.reg = 0x7b060,
-	.shift = 0,
-	.width = 2,
-	.safe_src_parent = P_BI_TCXO,
-	.parent_map = gcc_parent_map_4,
-	.clkr = {
-		.hw.init = &(struct clk_init_data){
-			.name = "gcc_pcie_0_pipe_clk_src",
-			.parent_data = gcc_parent_data_4,
-			.num_parents = ARRAY_SIZE(gcc_parent_data_4),
-			.ops = &clk_regmap_mux_safe_ops,
+static struct clk_regmap gcc_pcie_0_pipe_clk_src = {
+	.enable_reg = 0x7b060,
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_pcie_0_pipe_clk_src",
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pcie_0_pipe_clk",
 		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_phy_mux_ops,
 	},
 };
 
@@ -270,19 +245,16 @@  static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
 	},
 };
 
-static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
-	.reg = 0x9d064,
-	.shift = 0,
-	.width = 2,
-	.safe_src_parent = P_BI_TCXO,
-	.parent_map = gcc_parent_map_6,
-	.clkr = {
-		.hw.init = &(struct clk_init_data){
-			.name = "gcc_pcie_1_pipe_clk_src",
-			.parent_data = gcc_parent_data_6,
-			.num_parents = ARRAY_SIZE(gcc_parent_data_6),
-			.ops = &clk_regmap_mux_safe_ops,
+static struct clk_regmap gcc_pcie_1_pipe_clk_src = {
+	.enable_reg = 0x9d064,
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_pcie_1_pipe_clk_src",
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pcie_1_pipe_clk",
 		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_phy_mux_ops,
 	},
 };
 
@@ -1549,7 +1521,7 @@  static struct clk_branch gcc_pcie_0_pipe_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_pipe_clk",
 			.parent_data = &(const struct clk_parent_data){
-				.hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
+				.hw = &gcc_pcie_0_pipe_clk_src.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1690,7 +1662,7 @@  static struct clk_branch gcc_pcie_1_pipe_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_pipe_clk",
 			.parent_data = &(const struct clk_parent_data){
-				.hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
+				.hw = &gcc_pcie_1_pipe_clk_src.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -3024,7 +2996,7 @@  static struct clk_regmap *gcc_sm8450_clocks[] = {
 	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
 	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
 	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
-	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src,
 	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
 	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
 	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
@@ -3037,7 +3009,7 @@  static struct clk_regmap *gcc_sm8450_clocks[] = {
 	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
 	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
 	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
-	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
+	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src,
 	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
 	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
 	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,