@@ -18,15 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
-#define unsupported_encoding(s, insn) \
- do { \
- qemu_log_mask(LOG_UNIMP, \
- "%s:%d: unsupported instruction encoding 0x%08x " \
- "at pc=%016" PRIx64 "\n", \
- __FILE__, __LINE__, insn, s->pc_curr); \
- unallocated_encoding(s); \
- } while (0)
-
TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_local(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
@@ -2127,13 +2127,13 @@ static void disas_exc(DisasContext *s, uint32_t insn)
* with our 32-bit semihosting).
*/
if (s->current_el == 0) {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
break;
}
#endif
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
} else {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
}
break;
case 5:
@@ -2142,7 +2142,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
break;
}
/* DCPS1, DCPS2, DCPS3 */
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
break;
default:
unallocated_encoding(s);
@@ -2307,7 +2307,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
if (op3 != 0 || op4 != 0 || rn != 0x1f) {
goto do_unallocated;
} else {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
}
return;