diff mbox series

[v1,1/1] pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()

Message ID 20220516185500.32304-1-andriy.shevchenko@linux.intel.com
State Accepted
Commit 68aa84ff28ba5f5dfcb290b260600b0d61558703
Headers show
Series [v1,1/1] pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask() | expand

Commit Message

Andy Shevchenko May 16, 2022, 6:55 p.m. UTC
The callers already have dereferenced pointer to GPIO chip, no need to
do it again in chv_gpio_irq_mask_unmask(). Hence, replace IRQ data pointer
by GPIO chip pointer.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Mika Westerberg May 17, 2022, 10:07 a.m. UTC | #1
On Mon, May 16, 2022 at 09:55:00PM +0300, Andy Shevchenko wrote:
> The callers already have dereferenced pointer to GPIO chip, no need to
> do it again in chv_gpio_irq_mask_unmask(). Hence, replace IRQ data pointer
> by GPIO chip pointer.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko May 17, 2022, 4:34 p.m. UTC | #2
On Tue, May 17, 2022 at 01:07:27PM +0300, Mika Westerberg wrote:
> On Mon, May 16, 2022 at 09:55:00PM +0300, Andy Shevchenko wrote:
> > The callers already have dereferenced pointer to GPIO chip, no need to
> > do it again in chv_gpio_irq_mask_unmask(). Hence, replace IRQ data pointer
> > by GPIO chip pointer.
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Pushed to my review and testing queue, thanks!
diff mbox series

Patch

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index b696f9392789..26b2a425d201 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1255,9 +1255,8 @@  static void chv_gpio_irq_ack(struct irq_data *d)
 	raw_spin_unlock(&chv_lock);
 }
 
-static void chv_gpio_irq_mask_unmask(struct irq_data *d, irq_hw_number_t hwirq, bool mask)
+static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
 {
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 	u32 value, intr_line;
 	unsigned long flags;
@@ -1283,7 +1282,7 @@  static void chv_gpio_irq_mask(struct irq_data *d)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-	chv_gpio_irq_mask_unmask(d, hwirq, true);
+	chv_gpio_irq_mask_unmask(gc, hwirq, true);
 	gpiochip_disable_irq(gc, hwirq);
 }
 
@@ -1293,7 +1292,7 @@  static void chv_gpio_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	gpiochip_enable_irq(gc, hwirq);
-	chv_gpio_irq_mask_unmask(d, hwirq, false);
+	chv_gpio_irq_mask_unmask(gc, hwirq, false);
 }
 
 static unsigned chv_gpio_irq_startup(struct irq_data *d)