diff mbox series

[v4] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers

Message ID 20220503113246.13857-1-quic_tdas@quicinc.com
State Superseded
Headers show
Series [v4] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers | expand

Commit Message

Taniya Das May 3, 2022, 11:32 a.m. UTC 
Add the low pass audio clock controller device nodes. Keep the lpasscc
clock node disabled and enabled for lpass pil based devices.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
[v4]
 * Mark lpasscc[lpasscc@3000000] device node as "disabled".

[v3]
 * Fix unwanted extra spaces in reg property.
 * Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore>

 arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Comments

Stephen Boyd May 17, 2022, 8:31 a.m. UTC | #1 
Quoting Taniya Das (2022-05-03 22:35:29)
> Hello Stephen,
>
> On 5/4/2022 12:40 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2022-05-03 04:32:46)
> >> Add the low pass audio clock controller device nodes. Keep the lpasscc
> >> clock node disabled and enabled for lpass pil based devices.
> >
> > Does it mean that we're going to have overlapping reg ranges between
> > nodes in DT for clk controllers? That is not proper DT style, indicating
> > that we should combine the overlapping nodes and then have some
> > compatible or DT property telling us how to treat the clks in the audio
> > subsystem.
> >
>
> In the case where PIL based LPASS node would be used, we would disable
> the other lpass clock controller nodes. Does that seem fine or I would
> need to map the complete range in the current PIL driver if that works.
>

Is the idea that we would have a set of nodes that have overlapping reg
ranges but only one or the other would be enabled? That seems confusing.
Why don't we simply have one node that has a different compatible string
or some DT property that reflects the programming model of choice? Or
use the protected-clocks property to list out the clks that we don't
want to have registered on the system.

We shouldn't need to have two entirely different nodes for the same
physical device in the SoC, so talking about PIL based LPASS is
confusing. Can you explain further?
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f0b64be63c21..477a754741a1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,8 @@ 
 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -1978,6 +1980,48 @@ 
 			clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
 			clock-names = "iface";
 			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		lpass_audiocc: clock-controller@3300000 {
+			compatible = "qcom,sc7280-lpassaudiocc";
+			reg = <0 0x03300000 0 0x30000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+			       <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
+			clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
+			power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		lpass_aon: clock-controller@3380000 {
+			compatible = "qcom,sc7280-lpassaoncc";
+			reg = <0 0x03380000 0 0x30000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+			       <&rpmhcc RPMH_CXO_CLK_A>,
+			       <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+			clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		lpasscore: clock-controller@3900000 {
+			compatible = "qcom,sc7280-lpasscorecc";
+			reg = <0 0x03900000 0 0x50000>;
+			clocks =  <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		lpass_hm: clock-controller@3c00000 {
+			compatible = "qcom,sc7280-lpasshm";
+			reg = <0 0x3c00000 0 0x28>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
 		};

 		lpass_ag_noc: interconnect@3c40000 {