diff mbox

[ARM] Add support for Cortex-A35

Message ID 1447684941-37806-1-git-send-email-james.greenhalgh@arm.com
State New
Headers show

Commit Message

James Greenhalgh Nov. 16, 2015, 2:42 p.m. UTC 
Hi,

This patch adds support to the ARM back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flags for this CPU to FL_FOR_ARCH8A and FL_CRC32 and FL_LDSCHED,
in the same fashion as Cortex-A53 and Cortex-A57. While the Cortex-A35
has dual issue capabilities, we model it with an issue rate of one, with
the expectation that this will give better schedules when using the
Cortex-A53 pipeline model.

Bootstrapped with --with-tune=cortex-a35 with no issues.

I'm sorry to have this upstream a little late for the close of Stage 1,
I wanted to wait for binutils support to be committed. This happened
on Thursday [1]. If it is OK with the ARM maintainers, I'd like to get
this in to GCC 6.

OK?

Thanks,
James

[1]: https://sourceware.org/ml/binutils-cvs/2015-11/msg00065.html

---
2015-11-16  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-cores.def (cortex-a35): New.
	* config/arm/arm.c (arm_cortex_a35_tune): New.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add cortex-a35.
	* config/arm/t-aprofile: Likewise.
	* doc/invoke.texi (-mcpu): Likewise.

Comments

Kyrylo Tkachov Nov. 16, 2015, 5:18 p.m. UTC | #1 
On 16/11/15 14:42, James Greenhalgh wrote:
> Hi,

>

> This patch adds support to the ARM back-end for the Cortex-A35

> processor, as recently announced by ARM. The ARM Cortex-A35 provides

> full support for the ARMv8-A architecture, including the CRC extension,

> with optional Advanced-SIMD and Floating-Point support. We therefore set

> feature flags for this CPU to FL_FOR_ARCH8A and FL_CRC32 and FL_LDSCHED,

> in the same fashion as Cortex-A53 and Cortex-A57. While the Cortex-A35

> has dual issue capabilities, we model it with an issue rate of one, with

> the expectation that this will give better schedules when using the

> Cortex-A53 pipeline model.

>

> Bootstrapped with --with-tune=cortex-a35 with no issues.

>

> I'm sorry to have this upstream a little late for the close of Stage 1,

> I wanted to wait for binutils support to be committed. This happened

> on Thursday [1]. If it is OK with the ARM maintainers, I'd like to get

> this in to GCC 6.

>

> OK?

>

> Thanks,

> James

>

> [1]: https://sourceware.org/ml/binutils-cvs/2015-11/msg00065.html

>

> ---

> 2015-11-16  James Greenhalgh  <james.greenhalgh@arm.com>

>

> 	* config/arm/arm-cores.def (cortex-a35): New.

> 	* config/arm/arm.c (arm_cortex_a35_tune): New.

> 	* config/arm/arm-tables.opt: Regenerate.

> 	* config/arm/arm-tune.md: Regenerate.

> 	* config/arm/bpabi.h (BE8_LINK_SPEC): Add cortex-a35.

> 	* config/arm/t-aprofile: Likewise.

> 	* doc/invoke.texi (-mcpu): Likewise.

>


Ok.
Thanks,
Kyrill
diff mbox

Patch

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 86ed0cb..d09707b 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -165,6 +165,7 @@  ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_
 ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
 
 /* V8 Architecture Processors */
+ARM_CORE("cortex-a35",	cortexa35, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
 ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
 ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 41bf1ff..48aac41 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -304,6 +304,9 @@  EnumValue
 Enum(processor_type) String(cortex-a17.cortex-a7) Value(cortexa17cortexa7)
 
 EnumValue
+Enum(processor_type) String(cortex-a35) Value(cortexa35)
+
+EnumValue
 Enum(processor_type) String(cortex-a53) Value(cortexa53)
 
 EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index e56b5ad..1c84218 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -32,7 +32,7 @@ 
 	cortexr4f,cortexr5,cortexr7,
 	cortexm7,cortexm4,cortexm3,
 	marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
-	cortexa53,cortexa57,cortexa72,
-	exynosm1,qdf24xx,xgene1,
-	cortexa57cortexa53,cortexa72cortexa53"
+	cortexa35,cortexa53,cortexa57,
+	cortexa72,exynosm1,qdf24xx,
+	xgene1,cortexa57cortexa53,cortexa72cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e31be67..2c8de40 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1940,6 +1940,29 @@  const struct tune_params arm_cortex_a15_tune =
   tune_params::SCHED_AUTOPREF_FULL
 };
 
+const struct tune_params arm_cortex_a35_tune =
+{
+  arm_9e_rtx_costs,
+  &cortexa53_extra_costs,
+  NULL,					/* Sched adj cost.  */
+  arm_default_branch_cost,
+  &arm_default_vec_cost,
+  1,						/* Constant limit.  */
+  5,						/* Max cond insns.  */
+  8,						/* Memset max inline.  */
+  1,						/* Issue rate.  */
+  ARM_PREFETCH_NOT_BENEFICIAL,
+  tune_params::PREF_CONST_POOL_FALSE,
+  tune_params::PREF_LDRD_FALSE,
+  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* Thumb.  */
+  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* ARM.  */
+  tune_params::DISPARAGE_FLAGS_NEITHER,
+  tune_params::PREF_NEON_64_FALSE,
+  tune_params::PREF_NEON_STRINGOPS_TRUE,
+  FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
+  tune_params::SCHED_AUTOPREF_OFF
+};
+
 const struct tune_params arm_cortex_a53_tune =
 {
   arm_9e_rtx_costs,
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 8af4605..e522064 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@ 
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a17.cortex-a7				\
    |mcpu=marvell-pj4					\
+   |mcpu=cortex-a35					\
    |mcpu=cortex-a53					\
    |mcpu=cortex-a57					\
    |mcpu=cortex-a57.cortex-a53				\
@@ -94,6 +95,7 @@ 
    |mcpu=cortex-a12|mcpu=cortex-a17			\
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a17.cortex-a7				\
+   |mcpu=cortex-a35					\
    |mcpu=cortex-a53					\
    |mcpu=cortex-a57					\
    |mcpu=cortex-a57.cortex-a53				\
diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile
index e8b2aa3..7428ef0 100644
--- a/gcc/config/arm/t-aprofile
+++ b/gcc/config/arm/t-aprofile
@@ -86,6 +86,7 @@  MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a12
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a17
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a15.cortex-a7
 MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a17.cortex-a7
+MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a35
 MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a53
 MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57
 MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57.cortex-a53
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d782ab2..5ad9714 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13553,7 +13553,7 @@  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
-@samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
+@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
 @samp{cortex-r4},
 @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
 @samp{cortex-m4},