[37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC

Message ID	20220426163043.100432-38-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC Date: Tue, 26 Apr 2022 09:30:33 -0700 Message-Id: <20220426163043.100432-38-richard.henderson@linaro.org> In-Reply-To: <20220426163043.100432-1-richard.henderson@linaro.org> References: <20220426163043.100432-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Use tcg_constant \| expand [00/47] target/arm: Use tcg_constant [01/47] target/arm: Use tcg_constant in gen_probe_access [02/47] target/arm: Use tcg_constant in gen_mte_check* [03/47] target/arm: Use tcg_constant in gen_exception* [04/47] target/arm: Use tcg_constant in gen_adc_CC [05/47] target/arm: Use tcg_constant in handle_msr_i [06/47] target/arm: Use tcg_constant in handle_sys [07/47] target/arm: Use tcg_constant in disas_exc [08/47] target/arm: Use tcg_constant in gen_compare_and_swap_pair [09/47] target/arm: Use tcg_constant in disas_ld_lit [10/47] target/arm: Use tcg_constant in disas_ldst_* [11/47] target/arm: Use tcg_constant in disas_add_sum_imm* [12/47] target/arm: Use tcg_constant in disas_movw_imm [13/47] target/arm: Use tcg_constant in shift_reg_imm [14/47] target/arm: Use tcg_constant in disas_cond_select [15/47] target/arm: Use tcg_constant in handle_{rev16,crc32} [16/47] target/arm: Use tcg_constant in disas_data_proc_2src [17/47] target/arm: Use tcg_constant in disas_fp* [18/47] target/arm: Use tcg_constant in simd shift expanders [19/47] target/arm: Use tcg_constant in simd fp/int conversion [20/47] target/arm: Use tcg_constant in 2misc expanders [21/47] target/arm: Use tcg_constant in balance of translate-a64.c [22/47] target/arm: Use tcg_constant for aa32 exceptions [23/47] target/arm: Use tcg_constant for disas_iwmmxt_insn [24/47] target/arm: Use tcg_constant for gen_{msr,mrs} [25/47] target/arm: Use tcg_constant for vector shift expanders [26/47] target/arm: Use tcg_constant for do_coproc_insn [27/47] target/arm: Use tcg_constant for gen_srs [28/47] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot [29/47] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 [30/47] target/arm: Use tcg_constant for v7m MRS, MSR [31/47] target/arm: Use tcg_constant for TT, SAT, SMMLA [32/47] target/arm: Use tcg_constant in LDM, STM [33/47] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE [34/47] target/arm: Use tcg_constant in trans_CPS_v7m [35/47] target/arm: Use tcg_constant in trans_CSEL [36/47] target/arm: Use tcg_constant for trans_INDEX_* [37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC [38/47] target/arm: Use tcg_constant in FCPY, CPY [39/47] target/arm: Use tcg_constant in {incr, wrap}_last_active [40/47] target/arm: Use tcg_constant in do_clast_scalar [41/47] target/arm: Use tcg_constant in WHILE [42/47] target/arm: Use tcg_constant in LD1, ST1 [43/47] target/arm: Use tcg_constant in SUBR [44/47] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm [45/47] target/arm: Use tcg_constant for predicate descriptors [46/47] target/arm: Use tcg_constant for do_brk{2,3} [47/47] target/arm: Use tcg_constant for vector descriptor

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20220426163043.100432-38-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC
Date: Tue, 26 Apr 2022 09:30:33 -0700
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Series

target/arm: Use tcg_constant | expand

Comments

Peter Maydell April 28, 2022, 10:41 a.m. UTC | #1

On Tue, 26 Apr 2022 at 17:56, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 8b173f5c4a..9321457f31 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2103,9 +2103,7 @@  static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
             tcg_gen_ext32s_i64(reg, reg);
         }
     } else {
-        TCGv_i64 t = tcg_const_i64(inc);
-        do_sat_addsub_32(reg, t, a->u, a->d);
-        tcg_temp_free_i64(t);
+        do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d);
     }
     return true;
 }
@@ -2122,9 +2120,7 @@  static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
     TCGv_i64 reg = cpu_reg(s, a->rd);
 
     if (inc != 0) {
-        TCGv_i64 t = tcg_const_i64(inc);
-        do_sat_addsub_64(reg, t, a->u, a->d);
-        tcg_temp_free_i64(t);
+        do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d);
     }
     return true;
 }
@@ -2141,11 +2137,10 @@  static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
 
     if (inc != 0) {
         if (sve_access_check(s)) {
-            TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc);
             tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd),
                               vec_full_reg_offset(s, a->rn),
-                              t, fullsz, fullsz);
-            tcg_temp_free_i64(t);
+                              tcg_constant_i64(a->d ? -inc : inc),
+                              fullsz, fullsz);
         }
     } else {
         do_mov_z(s, a->rd, a->rn);
@@ -2165,9 +2160,8 @@  static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
 
     if (inc != 0) {
         if (sve_access_check(s)) {
-            TCGv_i64 t = tcg_const_i64(inc);
-            do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d);
-            tcg_temp_free_i64(t);
+            do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
+                              tcg_constant_i64(inc), a->u, a->d);
         }
     } else {
         do_mov_z(s, a->rd, a->rn);

[37/47] target/arm: Use tcg_constant in SINCDEC, INCDEC

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