@@ -45,7 +45,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get,
mt7915_implicit_txbf_set, "%lld\n");
/* test knob of system layer 1/2 error recovery */
-static int mt7915_ser_trigger_set(void *data, u64 val)
+static int mt7915_fw_ser_set(void *data, u64 val)
{
enum {
SER_SET_RECOVER_L1 = 1,
@@ -71,8 +71,47 @@ static int mt7915_ser_trigger_set(void *data, u64 val)
return ret;
}
-DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL,
- mt7915_ser_trigger_set, "%lld\n");
+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_ser, NULL,
+ mt7915_fw_ser_set, "%lld\n");
+
+static int
+mt7915_fw_ser_stats_show(struct seq_file *s, void *data)
+{
+ struct mt7915_dev *dev = s->private;
+ int ret;
+
+ /* grab firmware SER stats */
+ ret = mt7915_mcu_set_ser(dev, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ msleep(100);
+
+ seq_printf(s, "::E R , SER_STATUS = 0x%08x\n",
+ MT_SWDEF_SER_STATS);
+ seq_printf(s, "::E R , SER_PLE_ERR = 0x%08x\n",
+ MT_SWDEF_PLE_STATS);
+ seq_printf(s, "::E R , SER_PLE_ERR_1 = 0x%08x\n",
+ MT_SWDEF_PLE1_STATS);
+ seq_printf(s, "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n",
+ MT_SWDEF_PLE_AMSDU_STATS);
+ seq_printf(s, "::E R , SER_PSE_ERR = 0x%08x\n",
+ MT_SWDEF_PSE_STATS);
+ seq_printf(s, "::E R , SER_PSE_ERR_1 = 0x%08x\n",
+ MT_SWDEF_PSE1_STATS);
+ seq_printf(s, "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n",
+ MT_SWDEF_LAMC_WISR6_BN0_STATS);
+ seq_printf(s, "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n",
+ MT_SWDEF_LAMC_WISR6_BN1_STATS);
+ seq_printf(s, "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n",
+ MT_SWDEF_LAMC_WISR7_BN0_STATS);
+ seq_printf(s, "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n",
+ MT_SWDEF_LAMC_WISR7_BN1_STATS);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mt7915_fw_ser_stats);
static int
mt7915_radar_trigger(void *data, u64 val)
@@ -884,6 +923,8 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
debugfs_create_file("xmit-queues", 0400, dir, phy,
&mt7915_xmit_queues_fops);
debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops);
+ debugfs_create_file("fw_ser", 0200, dir, dev, &fops_fw_ser);
+ debugfs_create_file("fw_ser_stats", 0400, dir, dev, &mt7915_fw_ser_stats_fops);
debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin);
@@ -897,7 +938,6 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
&mt7915_rate_txpower_fops);
debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
mt7915_twt_stats);
- debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger);
if (!dev->dbdc_support || phy->band_idx) {
debugfs_create_u32("dfs_hw_pattern", 0400, dir,
&dev->hw_pattern);
@@ -2471,10 +2471,7 @@ int mt7915_mcu_init(struct mt7915_dev *dev)
/* force firmware operation mode into normal state,
* which should be set before firmware download stage.
*/
- if (is_mt7915(&dev->mt76))
- mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
- else
- mt76_wr(dev, MT_SWDEF_MODE_MT7916, MT_SWDEF_NORMAL_MODE);
+ mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
ret = mt7915_driver_own(dev, 0);
if (ret)
@@ -22,6 +22,7 @@ static const u32 mt7915_reg[] = {
[WFDMA_EXT_CSR_ADDR] = 0xd7000,
[CBTOP1_PHY_END] = 0x77ffffff,
[INFRA_MCU_ADDR_END] = 0x7c3fffff,
+ [SWDEF_BASE_ADDR] = 0x41f200,
};
static const u32 mt7916_reg[] = {
@@ -36,6 +37,7 @@ static const u32 mt7916_reg[] = {
[WFDMA_EXT_CSR_ADDR] = 0xd7000,
[CBTOP1_PHY_END] = 0x7fffffff,
[INFRA_MCU_ADDR_END] = 0x7c085fff,
+ [SWDEF_BASE_ADDR] = 0x411400,
};
static const u32 mt7986_reg[] = {
@@ -50,6 +52,7 @@ static const u32 mt7986_reg[] = {
[WFDMA_EXT_CSR_ADDR] = 0x27000,
[CBTOP1_PHY_END] = 0x7fffffff,
[INFRA_MCU_ADDR_END] = 0x7c085fff,
+ [SWDEF_BASE_ADDR] = 0x411400,
};
static const u32 mt7915_offs[] = {
@@ -30,6 +30,7 @@ enum reg_rev {
WFDMA_EXT_CSR_ADDR,
CBTOP1_PHY_END,
INFRA_MCU_ADDR_END,
+ SWDEF_BASE_ADDR,
__MT_REG_MAX,
};
@@ -929,12 +930,25 @@ enum offs_rev {
#define MT_ADIE_TYPE_MASK BIT(1)
/* FW MODE SYNC */
-#define MT_SWDEF_MODE 0x41f23c
-#define MT_SWDEF_MODE_MT7916 0x41143c
+#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR)
+
+#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
+#define MT_SWDEF_MODE MT_SWDEF(0x3c)
#define MT_SWDEF_NORMAL_MODE 0
#define MT_SWDEF_ICAP_MODE 1
#define MT_SWDEF_SPECTRUM_MODE 2
+#define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
+#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
+#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
+#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C)
+#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
+#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
+#define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
+#define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C)
+#define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060)
+#define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064)
+
#define MT_DIC_CMD_REG_BASE 0x41f000
#define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs))
#define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10)