diff mbox series

[v3,15/60] target/arm: Simplify gen_sar

Message ID 20220417174426.711829-16-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Cleanups, new features, new cpus | expand

Commit Message

Richard Henderson April 17, 2022, 5:43 p.m. UTC 
Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32.
Use tcg_constant_i32 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

Comments

Peter Maydell April 21, 2022, 6:57 p.m. UTC | #1 
On Sun, 17 Apr 2022 at 18:59, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32.
> Use tcg_constant_i32 while we're at it.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/translate.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 57631c9fa1..8d6534f9a5 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -568,12 +568,10 @@ GEN_SHIFT(shr)
>
>  static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
>  {
> -    TCGv_i32 tmp1, tmp2;
> -    tmp1 = tcg_temp_new_i32();
> +    TCGv_i32 tmp1 = tcg_temp_new_i32();
> +
>      tcg_gen_andi_i32(tmp1, t1, 0xff);
> -    tmp2 = tcg_const_i32(0x1f);
> -    tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1);
> -    tcg_temp_free_i32(tmp2);
> +    tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31));
>      tcg_gen_sar_i32(dest, t0, tmp1);
>      tcg_temp_free_i32(tmp1);
>  }

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 57631c9fa1..8d6534f9a5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -568,12 +568,10 @@  GEN_SHIFT(shr)
 
 static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
 {
-    TCGv_i32 tmp1, tmp2;
-    tmp1 = tcg_temp_new_i32();
+    TCGv_i32 tmp1 = tcg_temp_new_i32();
+
     tcg_gen_andi_i32(tmp1, t1, 0xff);
-    tmp2 = tcg_const_i32(0x1f);
-    tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1);
-    tcg_temp_free_i32(tmp2);
+    tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31));
     tcg_gen_sar_i32(dest, t0, tmp1);
     tcg_temp_free_i32(tmp1);
 }