| Message ID | 20220408080538.278707-2-Ajish.Koshy@microchip.com |
|---|---|
| State | New |
| Headers | show |
| Series | pm80xx updates | expand |
On Fri, Apr 8, 2022 at 10:05 AM Ajish Koshy <Ajish.Koshy@microchip.com> wrote: > > When upper inbound and outbound queues 32-63 are enabled, we see upper > vectors 32-63 in interrupt service routine. We need corresponding > registers to handle masking and unmasking of these upper interrupts. > > To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and > MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit > 0-31 represents interrupt vectors 32-63. > > Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com> > Signed-off-by: Viswas G <Viswas.G@microchip.com> > Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues") Acked-by: Jack Wang <jinpu.wang@ionos.com> > --- > drivers/scsi/pm8001/pm80xx_hwi.c | 30 ++++++++++++++++++++---------- > 1 file changed, 20 insertions(+), 10 deletions(-) > > diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c > index 9bb31f66db85..cdb31679f419 100644 > --- a/drivers/scsi/pm8001/pm80xx_hwi.c > +++ b/drivers/scsi/pm8001/pm80xx_hwi.c > @@ -1727,10 +1727,14 @@ static void > pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) > { > #ifdef PM8001_USE_MSIX > - u32 mask; > - mask = (u32)(1 << vec); > - > - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); > + if (vec < 32) { > + /* vectors 0 - 31 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); > + } else { > + /* vectors 32 - 63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, > + 1U << (vec - 32)); > + } > return; > #endif > pm80xx_chip_intx_interrupt_enable(pm8001_ha); > @@ -1746,12 +1750,18 @@ static void > pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) > { > #ifdef PM8001_USE_MSIX > - u32 mask; > - if (vec == 0xFF) > - mask = 0xFFFFFFFF; > - else > - mask = (u32)(1 << vec); > - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); > + if (vec == 0xFF) { > + /* disable all vectors 0-31, 32-63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); > + } else if (vec < 32) { > + /* vectors 0 - 31 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); > + } else { > + /* vectors 32 - 63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, > + 1U << (vec - 32)); > + } > return; > #endif > pm80xx_chip_intx_interrupt_disable(pm8001_ha); > -- > 2.31.1 >
On 08/04/2022 09:05, Ajish Koshy wrote: > When upper inbound and outbound queues 32-63 are enabled, we see upper > vectors 32-63 in interrupt service routine. We need corresponding > registers to handle masking and unmasking of these upper interrupts. > > To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and > MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit > 0-31 represents interrupt vectors 32-63. > > Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com> > Signed-off-by: Viswas G <Viswas.G@microchip.com> > Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues") Regardless of nitpick: Reviewed-by: John Garry <john.garry@huawei.com> > --- > drivers/scsi/pm8001/pm80xx_hwi.c | 30 ++++++++++++++++++++---------- > 1 file changed, 20 insertions(+), 10 deletions(-) > > diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c > index 9bb31f66db85..cdb31679f419 100644 > --- a/drivers/scsi/pm8001/pm80xx_hwi.c > +++ b/drivers/scsi/pm8001/pm80xx_hwi.c > @@ -1727,10 +1727,14 @@ static void > pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) comment on current code: using u8 for vec seems dubious > { > #ifdef PM8001_USE_MSIX > - u32 mask; > - mask = (u32)(1 << vec); > - > - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); > + if (vec < 32) { > + /* vectors 0 - 31 */ nit: I doubt the use of these sort of comments. I mean, a check for vec < 32 makes it pretty obvious > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); > + } else { > + /* vectors 32 - 63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, > + 1U << (vec - 32)); > + } > return; > #endif > pm80xx_chip_intx_interrupt_enable(pm8001_ha); > @@ -1746,12 +1750,18 @@ static void > pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) > { > #ifdef PM8001_USE_MSIX > - u32 mask; > - if (vec == 0xFF) > - mask = 0xFFFFFFFF; > - else > - mask = (u32)(1 << vec); > - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); > + if (vec == 0xFF) { > + /* disable all vectors 0-31, 32-63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); > + } else if (vec < 32) { > + /* vectors 0 - 31 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); > + } else { > + /* vectors 32 - 63 */ > + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, > + 1U << (vec - 32)); > + } > return; > #endif > pm80xx_chip_intx_interrupt_disable(pm8001_ha);
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 9bb31f66db85..cdb31679f419 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -1727,10 +1727,14 @@ static void pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) { #ifdef PM8001_USE_MSIX - u32 mask; - mask = (u32)(1 << vec); - - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); + if (vec < 32) { + /* vectors 0 - 31 */ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); + } else { + /* vectors 32 - 63 */ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, + 1U << (vec - 32)); + } return; #endif pm80xx_chip_intx_interrupt_enable(pm8001_ha); @@ -1746,12 +1750,18 @@ static void pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) { #ifdef PM8001_USE_MSIX - u32 mask; - if (vec == 0xFF) - mask = 0xFFFFFFFF; - else - mask = (u32)(1 << vec); - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); + if (vec == 0xFF) { + /* disable all vectors 0-31, 32-63 */ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); + } else if (vec < 32) { + /* vectors 0 - 31 */ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); + } else { + /* vectors 32 - 63 */ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, + 1U << (vec - 32)); + } return; #endif pm80xx_chip_intx_interrupt_disable(pm8001_ha);