Message ID | 20220408141550.1271295-39-peter.maydell@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | arm: Implement GICv4 | expand |
On 4/8/22 07:15, Peter Maydell wrote: > Now that we have implemented all the GICv4 requirements, relax the > error-checking on the GIC object's 'revision' property to allow a TCG > GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3. > > Our 'revision' property doesn't consider the possibility of wanting > to specify the minor version of the GIC -- for instance there is a > GICv3.1 which adds support for extended SPI and PPI ranges, among > other things, and also GICv4.1. But since the QOM property is > internal to QEMU, not user-facing, we can cross that bridge when we > come to it. Within the GIC implementation itself code generally > checks against the appropriate ID register feature bits, and the > only use of s->revision is for setting those ID register bits. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > hw/intc/arm_gicv3_common.c | 12 +++++++----- > hw/intc/arm_gicv3_kvm.c | 5 +++++ > 2 files changed, 12 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 181f342f32c..5634c6fc788 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -326,12 +326,14 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) GICv3State *s = ARM_GICV3_COMMON(dev); int i, rdist_capacity, cpuidx; - /* revision property is actually reserved and currently used only in order - * to keep the interface compatible with GICv2 code, avoiding extra - * conditions. However, in future it could be used, for example, if we - * implement GICv4. + /* + * This GIC device supports only revisions 3 and 4. The GICv1/v2 + * is a separate device. + * Note that subclasses of this device may impose further restrictions + * on the GIC revision: notably, the in-kernel KVM GIC doesn't + * support GICv4. */ - if (s->revision != 3) { + if (s->revision != 3 && s->revision != 4) { error_setg(errp, "unsupported GIC revision %d", s->revision); return; } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 5ec5ff9ef6e..06f5aceee52 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -781,6 +781,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) return; } + if (s->revision != 3) { + error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", + s->revision); + } + if (s->security_extn) { error_setg(errp, "the in-kernel VGICv3 does not implement the " "security extensions");
Now that we have implemented all the GICv4 requirements, relax the error-checking on the GIC object's 'revision' property to allow a TCG GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3. Our 'revision' property doesn't consider the possibility of wanting to specify the minor version of the GIC -- for instance there is a GICv3.1 which adds support for extended SPI and PPI ranges, among other things, and also GICv4.1. But since the QOM property is internal to QEMU, not user-facing, we can cross that bridge when we come to it. Within the GIC implementation itself code generally checks against the appropriate ID register feature bits, and the only use of s->revision is for setting those ID register bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gicv3_common.c | 12 +++++++----- hw/intc/arm_gicv3_kvm.c | 5 +++++ 2 files changed, 12 insertions(+), 5 deletions(-)