diff mbox series

[v2,09/16] crypto: qat - test PFVF registers for spurious interrupts on GEN4

Message ID 20220407165455.256777-10-marco.chiappero@intel.com
State Accepted
Commit 27c0f3a14f9fd16eed4e0167cf58225ca28ab4f8
Headers show
Series crypto: qat - misc fixes | expand

Commit Message

Marco Chiappero April 7, 2022, 4:54 p.m. UTC 
Spurious PFVF interrupts can happen when either the ISR is invoked
without a valid source being set or, otherwise, when no interrupt bit
is set in the PFVF register containing the message.

The latter test was present for GEN2 devices but missing for GEN4, this
patch fills the gap.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
---
 drivers/crypto/qat/qat_common/adf_gen4_pfvf.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c
index d80d493a7756..f7860bf612da 100644
--- a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c
+++ b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c
@@ -96,10 +96,16 @@  static struct pfvf_message adf_gen4_pfvf_recv(struct adf_accel_dev *accel_dev,
 					      u32 pfvf_offset, u8 compat_ver)
 {
 	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
+	struct pfvf_message msg = { 0 };
 	u32 csr_val;
 
 	/* Read message from the CSR */
 	csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);
+	if (!(csr_val & ADF_PFVF_INT)) {
+		dev_info(&GET_DEV(accel_dev),
+			 "Spurious PFVF interrupt, msg 0x%.8x. Ignored\n", csr_val);
+		return msg;
+	}
 
 	/* We can now acknowledge the message reception by clearing the
 	 * interrupt bit