@@ -149,12 +149,6 @@ static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
static void qcom_geni_serial_stop_rx(struct uart_port *uport);
static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
-static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
- 32000000, 48000000, 51200000, 64000000,
- 80000000, 96000000, 100000000,
- 102400000, 112000000, 120000000,
- 128000000};
-
#define to_dev_port(ptr, member) \
container_of(ptr, struct qcom_geni_serial_port, member)
@@ -946,32 +940,46 @@ static int qcom_geni_serial_startup(struct uart_port *uport)
return 0;
}
-static unsigned long get_clk_cfg(unsigned long clk_freq)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
- if (!(root_freq[i] % clk_freq))
- return root_freq[i];
- }
- return 0;
-}
-
-static unsigned long get_clk_div_rate(unsigned int baud,
+static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
unsigned int sampling_rate, unsigned int *clk_div)
{
unsigned long ser_clk;
unsigned long desired_clk;
+ unsigned long freq, prev, freq_first;
+
+ if (!clk) {
+ pr_err("%s: Invalid clock handle\n", __func__);
+ return 0;
+ }
desired_clk = baud * sampling_rate;
- ser_clk = get_clk_cfg(desired_clk);
- if (!ser_clk) {
- pr_err("%s: Can't find matching DFS entry for baud %d\n",
- __func__, baud);
- return ser_clk;
+ if (!desired_clk) {
+ pr_err("%s: Invalid frequency\n", __func__);
+ return 0;
}
+ freq_first = 0;
+ prev = desired_clk;
+ freq = desired_clk - 1;
+ do {
+ if (freq != (desired_clk - 1))
+ prev = freq;
+
+ freq = clk_round_rate(clk, (freq + 1));
+
+ if (!freq_first)
+ freq_first = freq;
+ } while ((freq % desired_clk) && (freq > 0) && (freq != prev));
+
+ if (!(freq % desired_clk))
+ ser_clk = freq;
+ else
+ ser_clk = freq_first;
+
*clk_div = ser_clk / desired_clk;
+ if ((ser_clk) && (!(*clk_div)))
+ *clk_div = 1;
+
return ser_clk;
}
@@ -1003,7 +1011,8 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
if (ver >= QUP_SE_VERSION_2_5)
sampling_rate /= 2;
- clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
+ clk_rate = get_clk_div_rate((port->se).clk, baud,
+ sampling_rate, &clk_div);
if (!clk_rate)
goto out_restart_rx;
[Why] This change is part of resolving feedback for an earlier patch. The UART frequency table is to be replaced with a call to clk_round_rate so it would work regardless of what the clk driver supports for the particular SoC. [How] Try to find a frequency and divider that exactly matches the required rate. If not found, return the closest possible frequency and set divider to 1. Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> --- drivers/tty/serial/qcom_geni_serial.c | 57 ++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 24 deletions(-)