diff mbox series

arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp

Message ID 20220318113526.15986-1-sherry.sun@nxp.com
State Accepted
Commit 68b7cf5d91d4c7e8a690693a53738e66d60113f1
Headers show
Series arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp | expand

Commit Message

Sherry Sun March 18, 2022, 11:35 a.m. UTC 
i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support
for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 794d75173cf5..a6124a11d6ee 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -902,6 +902,12 @@ 
 			interrupt-parent = <&gic>;
 		};
 
+		edacmc: memory-controller@3d400000 {
+			compatible = "snps,ddrc-3.80a";
+			reg = <0x3d400000 0x400000>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		ddr-pmu@3d800000 {
 			compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
 			reg = <0x3d800000 0x400000>;