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[net-next,v3,1/3] dt-bindings: net: mscc-miim: add lan966x compatible

Message ID 20220318201324.1647416-2-michael@walle.cc
State Accepted
Commit a2e4b5adfdf85d4a94af8a7a9f44e3ee254fd77e
Headers show
Series net: mscc-miim: add integrated PHY reset support | expand

Commit Message

Michael Walle March 18, 2022, 8:13 p.m. UTC 
The MDIO controller has support to release the internal PHYs from reset
by specifying a second memory resource. This is different between the
currently supported SparX-5 and the LAN966x. Add a new compatible to
distinguish between these two.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
 Documentation/devicetree/bindings/net/mscc-miim.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt
index 7104679cf59d..70e0cb1ee485 100644
--- a/Documentation/devicetree/bindings/net/mscc-miim.txt
+++ b/Documentation/devicetree/bindings/net/mscc-miim.txt
@@ -2,7 +2,7 @@  Microsemi MII Management Controller (MIIM) / MDIO
 =================================================
 
 Properties:
-- compatible: must be "mscc,ocelot-miim"
+- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"
 - reg: The base address of the MDIO bus controller register bank. Optionally, a
   second register bank can be defined if there is an associated reset register
   for internal PHYs