| Message ID | 20220317162349.739636-7-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Commit | a6d9efb62a482c2da1078d9654b68a0777aa2fc6 |
| Headers | show |
| Series | ARM: suniv: dts: update Allwinner F1C100 | expand |
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 922efd5e9457..0a7fa37bbd24 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -29,9 +29,13 @@ osc32k: clk-32k { }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; };
The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing the reg property, and the corresponding address and size cells properties. Add them to make the bindings check pass. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)