| Message ID | 20220315155919.23451-8-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | 6494e4f90503cb4027632dfcedcb7a683d829db0 |
| Headers | show |
| Series | Enable Ethernet and SDHI on RZ/G2UL SMARC EVK | expand |
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 7/7] arm64: dts: renesas: rzg2ul-smarc-som: Enable > Ethernet on SMARC platform > > Hi Biju, > > On Tue, Mar 15, 2022 at 4:59 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. > > > > Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and > > Ethernet0 device selection is based on the SW1[3] switch position. > > > > Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. > > Set SW1[3] to position ON for selecting Ethernet0. > > > > This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > > @@ -52,11 +57,101 @@ > > #endif > > }; > > > > +#if (!SW_ET0_EN_N) > > +ð0 { > > + pinctrl-0 = <ð0_pins>; > > + pinctrl-names = "default"; > > + phy-handle = <&phy0>; > > + phy-mode = "rgmii-id"; > > + status = "okay"; > > + > > + phy0: ethernet-phy@7 { > > + compatible = "ethernet-phy-id0022.1640", > > + "ethernet-phy-ieee802.3-c22"; > > To be augmented with interrupt properties when the RZ/G2L IRQC driver and > bindings have been completed. But that can be done later.. OK. Agreed. Cheers, Biju > > > + reg = <7>; > > + rxc-skew-psec = <2400>; > > + txc-skew-psec = <2400>; > > + rxdv-skew-psec = <0>; > > + txdv-skew-psec = <0>; > > + rxd0-skew-psec = <0>; > > + rxd1-skew-psec = <0>; > > + rxd2-skew-psec = <0>; > > + rxd3-skew-psec = <0>; > > + txd0-skew-psec = <0>; > > + txd1-skew-psec = <0>; > > + txd2-skew-psec = <0>; > > + txd3-skew-psec = <0>; > > + }; > > +}; > > +#endif > > + > > +ð1 { > > + pinctrl-0 = <ð1_pins>; > > + pinctrl-names = "default"; > > + phy-handle = <&phy1>; > > + phy-mode = "rgmii-id"; > > + status = "okay"; > > + > > + phy1: ethernet-phy@7 { > > + compatible = "ethernet-phy-id0022.1640", > > + "ethernet-phy-ieee802.3-c22"; > > + reg = <7>; > > Likewise. > > > + rxc-skew-psec = <2400>; > > + txc-skew-psec = <2400>; > > + rxdv-skew-psec = <0>; > > + txdv-skew-psec = <0>; > > + rxd0-skew-psec = <0>; > > + rxd1-skew-psec = <0>; > > + rxd2-skew-psec = <0>; > > + rxd3-skew-psec = <0>; > > + txd0-skew-psec = <0>; > > + txd1-skew-psec = <0>; > > + txd2-skew-psec = <0>; > > + txd3-skew-psec = <0>; > > + }; > > +}; > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 0d6fc0d84783..b0822679a55b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -9,8 +9,13 @@ #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; memory@48000000 { @@ -52,11 +57,101 @@ #endif }; +#if (!SW_ET0_EN_N) +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &extal_clk { clock-frequency = <24000000>; }; &pinctrl { + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */ + <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */ + <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */ + <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */ + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index b8caa833e349..81da096d0704 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -9,9 +9,11 @@ * DIP-Switch SW1 setting * 1 : High; 0: Low * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) * Please change below macros according to SW1 setting */ #define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi"
Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 97 ++++++++++++++++++- arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 2 + 2 files changed, 98 insertions(+), 1 deletion(-)