| Message ID | 1444921464-14895-6-git-send-email-will.deacon@arm.com |
|---|---|
| State | Accepted |
| Commit | c88ae5de71629e4b5e4075897d9980a7b079d122 |
| Headers | show
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[2001:1868:205::9]) by mx.google.com with ESMTPS id i9si7719880obe.79.2015.10.15.08.06.17 for <patch@linaro.org> (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 08:06:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zmk5g-0008P5-8d; Thu, 15 Oct 2015 15:05:12 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zmk5J-0006xW-In for linux-arm-kernel@lists.infradead.org; Thu, 15 Oct 2015 15:04:50 +0000 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.122]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id t9FF4MWr012668; Thu, 15 Oct 2015 16:04:22 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CD0B71AE3449; Thu, 15 Oct 2015 16:04:25 +0100 (BST) From: Will Deacon <will.deacon@arm.com> To: iommu@lists.linux-foundation.org Subject: [PATCH 5/6] iommu/arm-smmu: remove redundant calculation of gr0 base address Date: Thu, 15 Oct 2015 16:04:23 +0100 Message-Id: <1444921464-14895-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444921464-14895-1-git-send-email-will.deacon@arm.com> References: <1444921464-14895-1-git-send-email-will.deacon@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151015_080449_983262_BED0AD94 X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. 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diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 9aadf36a0747..7c20a68b5a95 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -709,9 +709,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; - void __iomem *cb_base, *gr0_base, *gr1_base; + void __iomem *cb_base, *gr1_base; - gr0_base = ARM_SMMU_GR0(smmu); gr1_base = ARM_SMMU_GR1(smmu); stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
Since commit 1463fe44fd0f ("iommu/arm-smmu: Don't use VMIDs for stage-1 translations"), we don't need the GR0 base address when initialising a context bank, so remove the useless local variable and its init code. Signed-off-by: Will Deacon <will.deacon@arm.com> --- drivers/iommu/arm-smmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)