[1/4] dt-bindings: cpufreq: mediatek: transform cpufreq-mediatek into yaml

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
new file mode 100644
index 000000000000..584946eb3790
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
@@ -0,0 +1,131 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek CPUFREQ driver Device Tree Bindings
+
+maintainers:
+  - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+
+description: |
+  CPUFREQ is used for scaling clock frequency of CPUs.
+  The module cooperates with CCI DEVFREQ to manage frequency for some Mediatek
+  SoCs.
+
+properties:
+  clocks:
+    items:
+      - description:
+          The first one is the multiplexer for clock input of CPU cluster.
+      - description:
+          The other is used as an intermediate clock source when the original
+          CPU is under transition and not stable yet.
+
+  clock-names:
+    items:
+      - const: "cpu"
+      - const: "intermediate"
+
+  operating-points-v2:
+    description:
+      For details, please refer to
+      Documentation/devicetree/bindings/opp/opp-v2.yaml
+
+  opp-table: true
+
+  proc-supply:
+    description:
+      Phandle of the regulator for CPU cluster that provides the supply
+      voltage.
+
+  sram-supply:
+    description:
+      Phandle of the regulator for sram of CPU cluster that provides the supply
+      voltage. When present, the cpufreq driver needs to do "voltage tracking"
+      to step by step scale up/down Vproc and Vsram to fit SoC specific needs.
+      When absent, the voltage scaling flow is handled by hardware, hence no
+      software "voltage tracking" is needed.
+
+  "#cooling-cells":
+    description:
+      For details, please refer to
+      Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
+
+required:
+  - clocks
+  - clock-names
+  - operating-points-v2
+  - proc-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    /* Example 1 (MT7623 SoC) */
+    #include <dt-bindings/clock/mt2701-clk.h>
+    cpu_opp_table: opp-table-0 {
+      compatible = "operating-points-v2";
+      opp-shared;
+      opp-598000000 {
+        opp-hz = /bits/ 64 <598000000>;
+        opp-microvolt = <1050000>;
+      };
+
+      /* ... */
+
+    };
+
+    cpus {
+      #address-cells = <2>;
+      #size-cells = <0>;
+      cpu0: cpu@0 {
+        device_type = "cpu";
+        compatible = "arm,cortex-a7";
+        reg = <0x0>;
+        clocks = <&infracfg CLK_INFRA_CPUSEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+        clock-names = "cpu", "intermediate";
+        operating-points-v2 = <&cpu_opp_table>;
+        proc-supply = <&mt6380_vcpu_reg>;
+        #cooling-cells = <2>;
+      };
+
+      /* ... */
+
+    };
+
+  - |
+    /* Example 2 (MT8173 SoC) */
+    #include <dt-bindings/clock/mt8173-clk.h>
+    cluster1_opp: opp-table-1 {
+      compatible = "operating-points-v2";
+      opp-shared;
+      opp-507000000 {
+        opp-hz = /bits/ 64 <507000000>;
+        opp-microvolt = <828000>;
+      };
+
+      /* ... */
+
+    };
+
+    cpus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      cpu2: cpu@100 {
+        device_type = "cpu";
+        compatible = "arm,cortex-a72";
+        reg = <0x100>;
+        enable-method = "psci";
+        cpu-idle-states = <&CPU_SLEEP_0>;
+        #cooling-cells = <2>;
+        clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+        clock-names = "cpu", "intermediate";
+        operating-points-v2 = <&cluster1_opp>;
+        proc-supply = <&mt6397_vpca15_reg>;
+      };
+
+      /* ... */
+
+    };