Message ID | 20220310112725.570053-12-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show
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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:38 -0800 (PST) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v5 11/48] target/nios2: Do not zero the general registers on reset Date: Thu, 10 Mar 2022 03:26:48 -0800 Message-Id: <20220310112725.570053-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
target/nios2: Shadow register set, EIC and VIC
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expand
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On Thu, 10 Mar 2022 at 11:27, Richard Henderson <richard.henderson@linaro.org> wrote: > > The bulk of the general register set is undefined on reset. They might be architecturally undefined, but for QEMU's purposes we want the state of the CPU on reset to be identical to the state it is in when QEMU is first started. thanks -- PMM
On 3/10/22 04:21, Peter Maydell wrote: > On Thu, 10 Mar 2022 at 11:27, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> The bulk of the general register set is undefined on reset. > > They might be architecturally undefined, but for QEMU's > purposes we want the state of the CPU on reset to be > identical to the state it is in when QEMU is first started. Ok, I've dropped this. The intent had been to remove a user/sysemu difference when we get to introducing shadow regs, but it isn't that big of a deal. r~
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 182ddcc18f..97bdc0a61b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,16 +53,16 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); - memset(env->regs, 0, sizeof(env->regs)); memset(env->ctrl, 0, sizeof(env->ctrl)); - env->pc = cpu->reset_addr; - #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; #else env->ctrl[CR_STATUS] = 0; #endif + + env->regs[R_ZERO] = 0; + env->pc = cpu->reset_addr; } #ifndef CONFIG_USER_ONLY
The bulk of the general register set is undefined on reset. The zero register is for the most part special-cased in translate, but the slot is still exposed to gdbstub and nios2_cpu_dump_state, so continue to make sure that's zeroed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/nios2/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)