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[2/3] dt-bindings: clock: Document MA35D1 clock controller bindings

Message ID 20220307091923.9909-3-ychuang3@nuvoton.com
State Superseded
Headers show
Series [1/3] dt-bindings: clock: add binding for MA35D1 clock controller | expand

Commit Message

Jacky Huang March 7, 2022, 9:19 a.m. UTC 
Add documentation to describe Nuvoton MA35D1 clock driver bindings.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 .../bindings/clock/nuvoton,ma35d1-clk.yaml    | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml

--
2.17.1
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Patch

diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
new file mode 100644
index 000000000000..f08b6f29bdcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
@@ -0,0 +1,66 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Clock Control Module Binding
+
+maintainers:
+  - Chi-Fang Li <cfli0@nuvoton.com>
+  - Jacky Huang <ychuang3@nuvoton.com>
+
+description: |
+  The MA35D1 clock controller generates clocks for the whole chip,
+  including system clocks and all peripheral clocks.
+
+  See also:
+    dt-bindings/clock/ma35d1-clk.h
+
+properties:
+  compatible:
+    const: nuvoton,ma35d1-clk
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  assigned-clocks:
+    maxItems: 4
+
+  assigned-clock-rates:
+    maxItems: 4
+
+  clock-pll-mode:
+    maxItems: 4
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - assigned-clocks
+  - assigned-clock-rates
+  - clock-pll-mode
+
+additionalProperties: false
+
+examples:
+  # clock control module node:
+  - |
+    clk: clock-controller@40460200 {
+        compatible = "nuvoton,ma35d1-clk";
+        reg = <0x00000000 0x40460200 0x0 0x100>;
+        #clock-cells = <1>;
+        assigned-clocks = <&clk DDRPLL>,
+                          <&clk APLL>,
+                          <&clk EPLL>,
+                          <&clk VPLL>;
+        assigned-clock-rates = <266000000>,
+                               <180000000>,
+                               <500000000>,
+                               <102000000>;
+        clock-pll-mode = <1>, <0>, <0>, <0>;
+    };
+...