@@ -21,7 +21,6 @@
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
#if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_2(mmu_read_debug, void, env, i32)
DEF_HELPER_3(mmu_write, void, env, i32, i32)
DEF_HELPER_1(check_interrupts, void, env)
#endif
@@ -44,7 +44,6 @@ void mmu_flip_um(CPUNios2State *env, unsigned int um);
unsigned int mmu_translate(CPUNios2State *env,
Nios2MMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
-void mmu_read_debug(CPUNios2State *env, uint32_t rn);
void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v);
void mmu_init(CPUNios2State *env);
@@ -35,26 +35,6 @@
#define MMU_LOG(x)
#endif
-void mmu_read_debug(CPUNios2State *env, uint32_t rn)
-{
- switch (rn) {
- case CR_TLBACC:
- MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn]));
- break;
-
- case CR_TLBMISC:
- MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn]));
- break;
-
- case CR_PTEADDR:
- MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn]));
- break;
-
- default:
- break;
- }
-}
-
/* rw - 0 = read, 1 = write, 2 = fetch. */
unsigned int mmu_translate(CPUNios2State *env,
Nios2MMULookup *lu,
@@ -26,11 +26,6 @@
#include "qemu/main-loop.h"
#if !defined(CONFIG_USER_ONLY)
-void helper_mmu_read_debug(CPUNios2State *env, uint32_t rn)
-{
- mmu_read_debug(env, rn);
-}
-
void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
mmu_write(env, rn, v);
@@ -448,23 +448,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
gen_check_supervisor(dc);
switch (instr.imm5 + CR_BASE) {
- case CR_PTEADDR:
- case CR_TLBACC:
- case CR_TLBMISC:
- {
-#if !defined(CONFIG_USER_ONLY)
- if (likely(instr.c != R_ZERO)) {
- tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]);
-#ifdef DEBUG_MMU
- TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE);
- gen_helper_mmu_read_debug(cpu_R[instr.c], cpu_env, tmp);
- tcg_temp_free_i32(tmp);
-#endif
- }
-#endif
- break;
- }
-
default:
if (likely(instr.c != R_ZERO)) {
tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]);