Message ID | 1444153590-24173-3-git-send-email-will.deacon@arm.com |
---|---|
State | Accepted |
Commit | fa7aae8a4257e6be7051420dac1f150c1eef721b |
Headers | show
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[2001:1868:205::9]) by mx.google.com with ESMTPS id v20si39648454wjq.123.2015.10.06.10.48.42 for <patch@linaro.org> (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 10:48:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjWKU-0008AI-JW; Tue, 06 Oct 2015 17:47:10 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjWKF-0007on-AM for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2015 17:46:56 +0000 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.122]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id t96HkVWr001365; Tue, 6 Oct 2015 18:46:31 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 2D5C31AE0FD7; Tue, 6 Oct 2015 18:46:32 +0100 (BST) From: Will Deacon <will.deacon@arm.com> To: catalin.marinas@arm.com Subject: [PATCH v2 02/10] arm64: proc: de-scope TLBI operation during cold boot Date: Tue, 6 Oct 2015 18:46:22 +0100 Message-Id: <1444153590-24173-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444153590-24173-1-git-send-email-will.deacon@arm.com> References: <1444153590-24173-1-git-send-email-will.deacon@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151006_104655_859641_0C5917AE X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. 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diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index e4ee7bd8830a..bbde13d77da5 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -146,8 +146,8 @@ ENDPROC(cpu_do_switch_mm) * value of the SCTLR_EL1 register. */ ENTRY(__cpu_setup) - tlbi vmalle1is // invalidate I + D TLBs - dsb ish + tlbi vmalle1 // Invalidate local TLB + dsb nsh mov x0, #3 << 20 msr cpacr_el1, x0 // Enable FP/ASIMD