| Message ID | 1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 2cabc45237659cb3b0294c8b8ae12f5fd0dad28d |
| Headers | show |
| Series | [v4,1/5] dt-bindings: clock: Add A7 PLL binding for SDX65 | expand |
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml index 8666e99..0e96f69 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -10,7 +10,7 @@ maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> description: - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high frequency clock to the CPU. properties:
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)