| Message ID | 20220216014505.28428-3-rex-bc.chen@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] dt-bindings: watchdog: Add compatible for MediaTek MT8186 | expand |
On Wed, 16 Feb 2022 09:45:03 +0800, Rex-BC Chen wrote: > From: Runyang Chen <runyang.chen@mediatek.com> > > Add toprgu reset-controller header file for MT8186. > > Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > include/dt-bindings/reset/mt8186-resets.h | 33 +++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 include/dt-bindings/reset/mt8186-resets.h > Acked-by: Rob Herring <robh@kernel.org>
On 2/15/22 17:45, Rex-BC Chen wrote: > From: Runyang Chen <runyang.chen@mediatek.com> > > Add toprgu reset-controller header file for MT8186. > > Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> With the next patch squashed into this one: Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > include/dt-bindings/reset/mt8186-resets.h | 33 +++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 include/dt-bindings/reset/mt8186-resets.h > > diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h > new file mode 100644 > index 000000000000..36e5764e2e6c > --- /dev/null > +++ b/include/dt-bindings/reset/mt8186-resets.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ > +/* > + * Copyright (c) 2022 MediaTek Inc. > + * Author: Runyang Chen <runyang.chen@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 > + > +#define MT8186_TOPRGU_INFRA_SW_RST 0 > +#define MT8186_TOPRGU_MM_SW_RST 1 > +#define MT8186_TOPRGU_MFG_SW_RST 2 > +#define MT8186_TOPRGU_VENC_SW_RST 3 > +#define MT8186_TOPRGU_VDEC_SW_RST 4 > +#define MT8186_TOPRGU_IMG_SW_RST 5 > +#define MT8186_TOPRGU_DDR_SW_RST 6 > +#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT8186_TOPRGU_CONNSYS_SW_RST 9 > +#define MT8186_TOPRGU_APMIXED_SW_RST 10 > +#define MT8186_TOPRGU_PWRAP_SW_RST 11 > +#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8186_TOPRGU_IPNNA_SW_RST 13 > +#define MT8186_TOPRGU_WPE_SW_RST 14 > +#define MT8186_TOPRGU_ADSP_SW_RST 15 > +#define MT8186_TOPRGU_AUDIO_SW_RST 17 > +#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 > +#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 > +#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 > +#define MT8186_TOPRGU_IPE_SW_RST 21 > +#define MT8186_TOPRGU_IMG2_SW_RST 22 > +#define MT8186_TOPRGU_SW_RST_NUM 23 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
Hello Guenter, Thanks for your review. I will do this in next version. BRs, Rex On Fri, 2022-02-25 at 08:37 -0800, Guenter Roeck wrote: > On 2/15/22 17:45, Rex-BC Chen wrote: > > From: Runyang Chen <runyang.chen@mediatek.com> > > > > Add toprgu reset-controller header file for MT8186. > > > > Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > With the next patch squashed into this one: > > Reviewed-by: Guenter Roeck <linux@roeck-us.net> > > > --- > > include/dt-bindings/reset/mt8186-resets.h | 33 > > +++++++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > create mode 100644 include/dt-bindings/reset/mt8186-resets.h > > > > diff --git a/include/dt-bindings/reset/mt8186-resets.h > > b/include/dt-bindings/reset/mt8186-resets.h > > new file mode 100644 > > index 000000000000..36e5764e2e6c > > --- /dev/null > > +++ b/include/dt-bindings/reset/mt8186-resets.h > > @@ -0,0 +1,33 @@ > > +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ > > +/* > > + * Copyright (c) 2022 MediaTek Inc. > > + * Author: Runyang Chen <runyang.chen@mediatek.com> > > + */ > > + > > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 > > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 > > + > > +#define MT8186_TOPRGU_INFRA_SW_RST 0 > > +#define MT8186_TOPRGU_MM_SW_RST > > 1 > > +#define MT8186_TOPRGU_MFG_SW_RST 2 > > +#define MT8186_TOPRGU_VENC_SW_RST 3 > > +#define MT8186_TOPRGU_VDEC_SW_RST 4 > > +#define MT8186_TOPRGU_IMG_SW_RST 5 > > +#define MT8186_TOPRGU_DDR_SW_RST 6 > > +#define MT8186_TOPRGU_INFRA_AO_SW_RST > > 8 > > +#define MT8186_TOPRGU_CONNSYS_SW_RST > > 9 > > +#define MT8186_TOPRGU_APMIXED_SW_RST > > 10 > > +#define MT8186_TOPRGU_PWRAP_SW_RST 11 > > +#define MT8186_TOPRGU_CONN_MCU_SW_RST > > 12 > > +#define MT8186_TOPRGU_IPNNA_SW_RST 13 > > +#define MT8186_TOPRGU_WPE_SW_RST 14 > > +#define MT8186_TOPRGU_ADSP_SW_RST 15 > > +#define MT8186_TOPRGU_AUDIO_SW_RST 17 > > +#define MT8186_TOPRGU_CAM_MAIN_SW_RST > > 18 > > +#define MT8186_TOPRGU_CAM_RAWA_SW_RST > > 19 > > +#define MT8186_TOPRGU_CAM_RAWB_SW_RST > > 20 > > +#define MT8186_TOPRGU_IPE_SW_RST 21 > > +#define MT8186_TOPRGU_IMG2_SW_RST 22 > > +#define MT8186_TOPRGU_SW_RST_NUM 23 > > + > > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ > >
diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h new file mode 100644 index 000000000000..36e5764e2e6c --- /dev/null +++ b/include/dt-bindings/reset/mt8186-resets.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Runyang Chen <runyang.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 + +#define MT8186_TOPRGU_INFRA_SW_RST 0 +#define MT8186_TOPRGU_MM_SW_RST 1 +#define MT8186_TOPRGU_MFG_SW_RST 2 +#define MT8186_TOPRGU_VENC_SW_RST 3 +#define MT8186_TOPRGU_VDEC_SW_RST 4 +#define MT8186_TOPRGU_IMG_SW_RST 5 +#define MT8186_TOPRGU_DDR_SW_RST 6 +#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 +#define MT8186_TOPRGU_CONNSYS_SW_RST 9 +#define MT8186_TOPRGU_APMIXED_SW_RST 10 +#define MT8186_TOPRGU_PWRAP_SW_RST 11 +#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8186_TOPRGU_IPNNA_SW_RST 13 +#define MT8186_TOPRGU_WPE_SW_RST 14 +#define MT8186_TOPRGU_ADSP_SW_RST 15 +#define MT8186_TOPRGU_AUDIO_SW_RST 17 +#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 +#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 +#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 +#define MT8186_TOPRGU_IPE_SW_RST 21 +#define MT8186_TOPRGU_IMG2_SW_RST 22 +#define MT8186_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */