diff mbox

[ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is on

Message ID 55F14744.1070907@arm.com
State Accepted
Commit 9b9828886e093b6f41b3abf8fd999e6817e2292c
Headers show

Commit Message

Kyrylo Tkachov Sept. 10, 2015, 9:03 a.m. UTC
Hi all,

The ICE in this PR occurs when trying to compile code containing half-precision FP operations
for Thumb2 with -mrestrict-it and an -mfpu that does not support fp16 (-mfpu=neon or lower).

The problem is that we disable for -mrestrict-it the *arm32_movhf pattern that performs the move using only
the general regs.

Instead what we should do is allow the pattern to match but forbid its predication for -mrestrict-it
by using the predicable_short_it attribute.

This fixes the ICE.

Bootstrap and test on arm is ok.
This bug appears on the 5 and 4.9 branches as well.
Ok for all active branches if testing there comes clean?

Thanks,
Kyrill

2015-09-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     PR target/67439
     * config/arm/arm.md (*arm32_movhf): Remove !arm_restrict_it from
     predicate.  Set predicable_short_it attr to "no".

2015-09-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     PR target/67439
     * gcc.target/arm/pr67439_1.c: New test.

Comments

Ramana Radhakrishnan Sept. 10, 2015, 9:54 a.m. UTC | #1
On Thu, Sep 10, 2015 at 10:03 AM, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
> Hi all,
>
> The ICE in this PR occurs when trying to compile code containing
> half-precision FP operations
> for Thumb2 with -mrestrict-it and an -mfpu that does not support fp16
> (-mfpu=neon or lower).
>
> The problem is that we disable for -mrestrict-it the *arm32_movhf pattern
> that performs the move using only
> the general regs.
>
> Instead what we should do is allow the pattern to match but forbid its
> predication for -mrestrict-it
> by using the predicable_short_it attribute.
>
> This fixes the ICE.
>
> Bootstrap and test on arm is ok.
> This bug appears on the 5 and 4.9 branches as well.
> Ok for all active branches if testing there comes clean?

OK if no regressions,

Thanks,
Ramana

>
> Thanks,
> Kyrill
>
> 2015-09-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     PR target/67439
>     * config/arm/arm.md (*arm32_movhf): Remove !arm_restrict_it from
>     predicate.  Set predicable_short_it attr to "no".
>
> 2015-09-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     PR target/67439
>     * gcc.target/arm/pr67439_1.c: New test.
diff mbox

Patch

commit b4888a0a5a9d2be30f99162a22ba2f22af46cbcd
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Sep 3 13:47:38 2015 +0100

    [ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is on

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 896deeb..fca9491 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6542,7 +6542,7 @@  (define_expand "movhf"
 (define_insn "*arm32_movhf"
   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
 	(match_operand:HF 1 "general_operand"	   " m,r,r,F"))]
-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && !arm_restrict_it
+  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
    && (	  s_register_operand (operands[0], HFmode)
        || s_register_operand (operands[1], HFmode))"
   "*
@@ -6580,7 +6580,8 @@  (define_insn "*arm32_movhf"
   [(set_attr "conds" "unconditional")
    (set_attr "type" "load1,store1,mov_reg,multiple")
    (set_attr "length" "4,4,4,8")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")]
 )
 
 (define_expand "movsf"
diff --git a/gcc/testsuite/gcc.target/arm/pr67439_1.c b/gcc/testsuite/gcc.target/arm/pr67439_1.c
new file mode 100644
index 0000000..f7a6128
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr67439_1.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O1 -mfp16-format=ieee -march=armv7-a -mfpu=neon -mthumb -mrestrict-it" } */
+
+__fp16 h0 = -1.0;
+
+void
+f (__fp16 *p)
+{
+  h0 = 1.0;
+}