@@ -101,14 +101,14 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
goto err;
}
- /* DSP is powered up, set all SSPs to slave mode */
+ /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */
for (i = 0; i < chip->ssp_count; i++) {
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
chip->ssp_base_offset
+ i * SSP_DEV_MEM_SIZE
+ SSP_SSC1_OFFSET,
- SSP_SET_SLAVE,
- SSP_SET_SLAVE);
+ SSP_SET_CBP_CFP,
+ SSP_SET_CBP_CFP);
}
/* step 2: purge FW request */
@@ -383,9 +383,9 @@
/* SSP Registers */
#define SSP_SSC1_OFFSET 0x4
-#define SSP_SET_SCLK_SLAVE BIT(25)
-#define SSP_SET_SFRM_SLAVE BIT(24)
-#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
+#define SSP_SET_SCLK_CONSUMER BIT(25)
+#define SSP_SET_SFRM_CONSUMER BIT(24)
+#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
#define HDA_IDISP_ADDR 2
#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))