diff mbox series

[PULL,14/38] hw/intc/arm_gic: Implement read of GICC_IIDR

Message ID 20220120123630.267975-15-peter.maydell@linaro.org
State Accepted
Commit a66a24585fae7036dc2f358c9addd1630be5c50c
Headers show
Series [PULL,01/38] hw/arm/virt: KVM: Enable PAuth when supported by the host | expand

Commit Message

Peter Maydell Jan. 20, 2022, 12:36 p.m. UTC 
From: Petr Pavlu <petr.pavlu@suse.com>

Implement support for reading GICC_IIDR. This register is used by the
Linux kernel to recognize that GICv2 with GICC_APRn is present.

Signed-off-by: Petr Pavlu <petr.pavlu@suse.com>
Message-id: 20220113151916.17978-2-ppavlu@suse.cz
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index a994b1f0245..0cd9ceca8d1 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1662,6 +1662,15 @@  static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
         }
         break;
     }
+    case 0xfc:
+        if (s->revision == REV_11MPCORE) {
+            /* Reserved on 11MPCore */
+            *data = 0;
+        } else {
+            /* GICv1 or v2; Arm implementation */
+            *data = (s->revision << 16) | 0x43b;
+        }
+        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gic_cpu_read: Bad offset %x\n", (int)offset);