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[PULL,05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts

Message ID 1441731092-6513-6-git-send-email-peter.maydell@linaro.org
State Accepted
Commit d5523a13656fb8df902a15a9fd8bd652b85e97e0
Headers show

Commit Message

Peter Maydell Sept. 8, 2015, 4:51 p.m. UTC 
Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1438089748-5528-6-git-send-email-peter.maydell@linaro.org
---
 hw/intc/arm_gic.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 9daa8cd..2df550c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -262,6 +262,7 @@  static void gic_activate_irq(GICState *s, int cpu, int irq)
     }
 
     s->running_priority[cpu] = prio;
+    GIC_SET_ACTIVE(irq, 1 << cpu);
 }
 
 static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -536,6 +537,7 @@  void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
      */
 
     gic_drop_prio(s, cpu, group);
+    GIC_CLEAR_ACTIVE(irq, cm);
     gic_update(s);
 }