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[PULL,25/27] i.MX: Add i2C devices to i.MX31 SOC

Message ID 1441379156-23939-26-git-send-email-peter.maydell@linaro.org
State Accepted
Commit d4e26d106a1ea35a81176cb5398406b08316adc7
Headers show

Commit Message

Peter Maydell Sept. 4, 2015, 3:05 p.m. UTC 
From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx31.c         | 30 ++++++++++++++++++++++++++++++
 include/hw/arm/fsl-imx31.h | 11 +++++++++++
 2 files changed, 41 insertions(+)
diff mbox

Patch

diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index 1681ecf..87548c8 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -50,6 +50,11 @@  static void fsl_imx31_init(Object *obj)
         object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
         qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
+        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
+    }
 }
 
 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
@@ -154,6 +159,31 @@  static void fsl_imx31_realize(DeviceState *dev, Error **errp)
                                             epit_table[i].irq));
     }
 
+    /* Initialize all I2C */
+    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+        static const struct {
+            hwaddr addr;
+            unsigned int irq;
+        } i2c_table[FSL_IMX31_NUM_I2CS] = {
+            { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
+            { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
+            { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
+        };
+
+        /* Initialize the I2C */
+        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        /* Map I2C memory */
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
+        /* Connect I2C IRQ to PIC */
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->avic),
+                                            i2c_table[i].irq));
+    }
+
     /* On a real system, the first 16k is a `secure boot rom' */
     memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
                                   "imx31.secure_rom",
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index 128006f..891166f 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -31,6 +31,7 @@ 
 
 #define FSL_IMX31_NUM_UARTS 2
 #define FSL_IMX31_NUM_EPITS 2
+#define FSL_IMX31_NUM_I2CS 3
 
 typedef struct FslIMX31State {
     /*< private >*/
@@ -43,6 +44,7 @@  typedef struct FslIMX31State {
     IMXSerialState uart[FSL_IMX31_NUM_UARTS];
     IMXGPTState    gpt;
     IMXEPITState   epit[FSL_IMX31_NUM_EPITS];
+    IMXI2CState    i2c[FSL_IMX31_NUM_I2CS];
     MemoryRegion   secure_rom;
     MemoryRegion   rom;
     MemoryRegion   iram;
@@ -57,10 +59,16 @@  typedef struct FslIMX31State {
 #define FSL_IMX31_IRAM_ALIAS_SIZE       0xFFC0000
 #define FSL_IMX31_IRAM_ADDR             0x1FFFC000
 #define FSL_IMX31_IRAM_SIZE             0x4000
+#define FSL_IMX31_I2C1_ADDR             0x43F80000
+#define FSL_IMX31_I2C1_SIZE             0x4000
+#define FSL_IMX31_I2C3_ADDR             0x43F84000
+#define FSL_IMX31_I2C3_SIZE             0x4000
 #define FSL_IMX31_UART1_ADDR            0x43F90000
 #define FSL_IMX31_UART1_SIZE            0x4000
 #define FSL_IMX31_UART2_ADDR            0x43F94000
 #define FSL_IMX31_UART2_SIZE            0x4000
+#define FSL_IMX31_I2C2_ADDR             0x43F98000
+#define FSL_IMX31_I2C2_SIZE             0x4000
 #define FSL_IMX31_CCM_ADDR              0x53F80000
 #define FSL_IMX31_CCM_SIZE              0x4000
 #define FSL_IMX31_GPT_ADDR              0x53F90000
@@ -95,5 +103,8 @@  typedef struct FslIMX31State {
 #define FSL_IMX31_GPT_IRQ               29
 #define FSL_IMX31_UART2_IRQ             32
 #define FSL_IMX31_UART1_IRQ             45
+#define FSL_IMX31_I2C1_IRQ              10
+#define FSL_IMX31_I2C2_IRQ              4
+#define FSL_IMX31_I2C3_IRQ              3
 
 #endif /* FSL_IMX31_H */