| Message ID | 20220102115356.75796-5-krzysztof.kozlowski@canonical.com |
|---|---|
| State | Accepted |
| Commit | c47db13bdf66b32bf2da8e561c13cc1253268b16 |
| Headers | show |
| Series | None | expand |
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml index f3fa6c7ef48b..599baf0b7231 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml @@ -209,14 +209,17 @@ allOf: then: properties: clocks: - minItems: 4 - maxItems: 4 + minItems: 7 + maxItems: 7 clock-names: items: - const: fin_pll - const: dout_aclk_fsys1_200 - const: dout_sclk_mmc0 - const: dout_sclk_mmc1 + - const: dout_sclk_ufsunipro20 + - const: dout_sclk_phy_fsys1 + - const: dout_sclk_phy_fsys1_26m required: - clock-names - clocks
The UFS for Exynos7 SoC clock controller requires additional input clocks for the FSYS1 clock controller. Update the bindings to reflect this, at least in theory. In practice, these input clocks are ignored, so it is rather adjusting of bindings to existing DTS, without affecting any real users. I understand that is not how it should be done, though... Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- .../devicetree/bindings/clock/samsung,exynos7-clock.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)