commit 771d788b184d466d1ea9fad87ab200601421f8c0
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Mon Jul 27 15:02:38 2015 +0100
[AArch64][2/3] Implement negcc, notcc optabs
@@ -3038,6 +3038,24 @@ (define_expand "mov<mode>cc"
}
)
+(define_expand "<neg_not_op><mode>cc"
+ [(set (match_operand:GPI 0 "register_operand" "")
+ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
+ (NEG_NOT:GPI (match_operand:GPI 2 "register_operand" ""))
+ (match_operand:GPI 3 "register_operand" "")))]
+ ""
+ {
+ rtx ccreg;
+ enum rtx_code code = GET_CODE (operands[1]);
+
+ if (code == UNEQ || code == LTGT)
+ FAIL;
+
+ ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ }
+)
;; CRC32 instructions.
(define_insn "aarch64_<crc_variant>"
@@ -668,6 +668,9 @@ (define_code_iterator LOGICAL [and ior xor])
;; Code iterator for logical operations whose :nlogical works on SIMD registers.
(define_code_iterator NLOGICAL [and ior])
+;; Code iterator for unary negate and bitwise complement.
+(define_code_iterator NEG_NOT [neg not])
+
;; Code iterator for sign/zero extension
(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
@@ -797,6 +800,9 @@ (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
;; Logical operator instruction mnemonics
(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
+;; Operation names for negate and bitwise complement.
+(define_code_attr neg_not_op [(neg "neg") (not "not")])
+
;; Similar, but when not(op)
(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
new file mode 100644
@@ -0,0 +1,99 @@
+/* { dg-do run } */
+/* { dg-options "-save-temps -O2 -fno-inline" } */
+
+extern void abort (void);
+
+#define N 30
+#define M 25089992
+
+int
+foonegsi (int a)
+{
+ return a ? N : -N;
+}
+
+/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*" } } */
+
+
+int
+fooinvsi (int a)
+{
+ return a ? N : ~N;
+}
+
+/* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*" } } */
+
+
+long long
+foonegdi (long long a)
+{
+ return a ? N : -N;
+}
+
+long long
+largefooneg (long long a)
+{
+ return a ? M : -M;
+}
+
+/* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*" } } */
+
+long long
+fooinvdi (long long a)
+{
+ return a ? N : ~N;
+}
+
+long long
+largefooinv (long long a)
+{
+ return a ? M : ~M;
+}
+
+/* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*" } } */
+
+
+int
+main (void)
+{
+ if (foonegsi (1) != N)
+ abort ();
+
+ if (foonegsi (0) != -N)
+ abort ();
+
+ if (fooinvsi (1) != N)
+ abort ();
+
+ if (fooinvsi (0) != ~N)
+ abort ();
+
+ if (foonegdi (1) != N)
+ abort ();
+
+ if (foonegdi (0) != -N)
+ abort ();
+
+ if (fooinvdi (1) != N)
+ abort ();
+
+ if (fooinvdi (0) != ~N)
+ abort ();
+
+ if (largefooinv (0) != ~M)
+ abort ();
+
+ if (largefooneg (0) != -M)
+ abort ();
+
+ if (largefooinv (1) != M)
+ abort ();
+
+ if (largefooneg (1) != M)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not "csel\tx\[0-9\]*.*" } } */
+/* { dg-final { scan-assembler-not "csel\tw\[0-9\]*.*" } } */
Hi all, This second patch implements the new optabs for aarch64. The new expander is almost identical to the mov<mode>cc expander except that operand 2 has a neg or a not before it to reflect the fact that it should be negated if the comparison in operand 1 holds. These patterns will eventually match to the CSNEG and CSINV instructions. The test included shows the kind of code that triggers this. We will now create a single immediate move followed by a CSNEG (or CSINV) rather than performing two immediate moves followed by a CSEL. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk if the midend changes in 1/3 are approved? Thanks, Kyrill 2015-09-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64.md (<neg_not_op><mode>cc): New define_expand. * config/aarch64/iterators.md (NEG_NOT): New code iterator. (neg_not_op): New code attribute. 2015-09-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.target/aarch64/cond_op_imm_1.c: New test.