@@ -212,7 +212,8 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id,
goto free_irq_vectors;
}
- hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
+ hcd->amd_resume_bug = (IS_ENABLED(CONFIG_USB_PCI_AMD) &&
+ usb_hcd_amd_remote_wakeup_quirk(dev) &&
driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
if (driver->flags & HCD_MEMORY) {
@@ -369,7 +369,7 @@ config USB_ISP116X_HCD
config USB_ISP1362_HCD
tristate "ISP1362 HCD support"
- depends on HAS_IOMEM
+ depends on HAS_IOPORT
depends on COMPILE_TEST # nothing uses this
help
Supports the Philips ISP1362 chip as a host controller
@@ -605,7 +605,7 @@ endif # USB_OHCI_HCD
config USB_UHCI_HCD
tristate "UHCI HCD (most Intel and VIA) support"
- depends on USB_PCI || USB_UHCI_SUPPORT_NON_PCI_HC
+ depends on (USB_PCI && HAS_IOPORT) || USB_UHCI_SUPPORT_NON_PCI_HC
help
The Universal Host Controller Interface is a standard by Intel for
accessing the USB hardware in the PC (which is also called the USB
@@ -60,6 +60,23 @@
#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
+/* ASMEDIA quirk use */
+#define ASMT_DATA_WRITE0_REG 0xF8
+#define ASMT_DATA_WRITE1_REG 0xFC
+#define ASMT_CONTROL_REG 0xE0
+#define ASMT_CONTROL_WRITE_BIT 0x02
+#define ASMT_WRITEREG_CMD 0x10423
+#define ASMT_FLOWCTL_ADDR 0xFA30
+#define ASMT_FLOWCTL_DATA 0xBA
+#define ASMT_PSEUDO_DATA 0
+
+/* Intel quirk use */
+#define USB_INTEL_XUSB2PR 0xD0
+#define USB_INTEL_USB2PRM 0xD4
+#define USB_INTEL_USB3_PSSEN 0xD8
+#define USB_INTEL_USB3PRM 0xDC
+
+#ifdef CONFIG_USB_PCI_AMD
/* AMD quirk use */
#define AB_REG_BAR_LOW 0xe0
#define AB_REG_BAR_HIGH 0xe1
@@ -93,21 +110,6 @@
#define NB_PIF0_PWRDOWN_0 0x01100012
#define NB_PIF0_PWRDOWN_1 0x01100013
-#define USB_INTEL_XUSB2PR 0xD0
-#define USB_INTEL_USB2PRM 0xD4
-#define USB_INTEL_USB3_PSSEN 0xD8
-#define USB_INTEL_USB3PRM 0xDC
-
-/* ASMEDIA quirk use */
-#define ASMT_DATA_WRITE0_REG 0xF8
-#define ASMT_DATA_WRITE1_REG 0xFC
-#define ASMT_CONTROL_REG 0xE0
-#define ASMT_CONTROL_WRITE_BIT 0x02
-#define ASMT_WRITEREG_CMD 0x10423
-#define ASMT_FLOWCTL_ADDR 0xFA30
-#define ASMT_FLOWCTL_DATA 0xBA
-#define ASMT_PSEUDO_DATA 0
-
/*
* amd_chipset_gen values represent AMD different chipset generations
*/
@@ -460,50 +462,6 @@ void usb_amd_quirk_pll_disable(void)
}
EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
-static int usb_asmedia_wait_write(struct pci_dev *pdev)
-{
- unsigned long retry_count;
- unsigned char value;
-
- for (retry_count = 1000; retry_count > 0; --retry_count) {
-
- pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
-
- if (value == 0xff) {
- dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
- return -EIO;
- }
-
- if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
- return 0;
-
- udelay(50);
- }
-
- dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
- return -ETIMEDOUT;
-}
-
-void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
-{
- if (usb_asmedia_wait_write(pdev) != 0)
- return;
-
- /* send command and address to device */
- pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
- pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
- pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
-
- if (usb_asmedia_wait_write(pdev) != 0)
- return;
-
- /* send data to device */
- pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
- pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
- pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
-}
-EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
-
void usb_amd_quirk_pll_enable(void)
{
usb_amd_quirk_pll(0);
@@ -632,7 +590,52 @@ bool usb_amd_pt_check_port(struct device *device, int port)
return !(value & BIT(port_shift));
}
EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
+#endif
+static int usb_asmedia_wait_write(struct pci_dev *pdev)
+{
+ unsigned long retry_count;
+ unsigned char value;
+
+ for (retry_count = 1000; retry_count > 0; --retry_count) {
+ pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
+
+ if (value == 0xff) {
+ dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
+ return -EIO;
+ }
+
+ if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
+ return 0;
+
+ udelay(50);
+ }
+
+ dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
+ return -ETIMEDOUT;
+}
+
+void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
+{
+ if (usb_asmedia_wait_write(pdev) != 0)
+ return;
+
+ /* send command and address to device */
+ pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
+ pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
+ pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
+
+ if (usb_asmedia_wait_write(pdev) != 0)
+ return;
+
+ /* send data to device */
+ pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
+ pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
+ pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
+}
+EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
+
+#if IS_ENABLED(CONFIG_USB_UHCI_HCD) && defined(CONFIG_HAS_IOPORT)
/*
* Make sure the controller is completely inactive, unable to
* generate interrupts or do DMA.
@@ -713,6 +716,7 @@ int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
return 1;
}
EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
+#endif
static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
{
@@ -728,7 +732,7 @@ static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
unsigned long base = 0;
int i;
- if (!pio_enabled(pdev))
+ if (!IS_ENABLED(CONFIG_HAS_IOPORT) || !pio_enabled(pdev))
return;
for (i = 0; i < PCI_STD_NUM_BARS; i++)
@@ -1273,7 +1277,8 @@ static void quirk_usb_early_handoff(struct pci_dev *pdev)
"Can't enable PCI device, BIOS handoff failed.\n");
return;
}
- if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
+ if (IS_ENABLED(CONFIG_USB_UHCI_HCD) &&
+ pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
quirk_usb_handoff_uhci(pdev);
else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
quirk_usb_handoff_ohci(pdev);
@@ -2,33 +2,50 @@
#ifndef __LINUX_USB_PCI_QUIRKS_H
#define __LINUX_USB_PCI_QUIRKS_H
-#ifdef CONFIG_USB_PCI
void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
-int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev);
+
+struct pci_dev;
+
+#ifdef CONFIG_USB_PCI_AMD
bool usb_amd_hang_symptom_quirk(void);
bool usb_amd_prefetch_quirk(void);
void usb_amd_dev_put(void);
bool usb_amd_quirk_pll_check(void);
void usb_amd_quirk_pll_disable(void);
void usb_amd_quirk_pll_enable(void);
-void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev);
-void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev);
-void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
void sb800_prefetch(struct device *dev, int on);
bool usb_amd_pt_check_port(struct device *device, int port);
#else
-struct pci_dev;
+static inline bool usb_amd_hang_symptom_quirk(void)
+{
+ return false;
+};
+static inline bool usb_amd_prefetch_quirk(void)
+{
+ return false;
+}
+static inline bool usb_amd_quirk_pll_check(void)
+{
+ return false;
+}
static inline void usb_amd_quirk_pll_disable(void) {}
static inline void usb_amd_quirk_pll_enable(void) {}
-static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}
static inline void usb_amd_dev_put(void) {}
-static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
static inline void sb800_prefetch(struct device *dev, int on) {}
static inline bool usb_amd_pt_check_port(struct device *device, int port)
{
return false;
}
+#endif /* CONFIG_USB_PCI_AMD */
+
+#ifdef CONFIG_USB_PCI
+void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev);
+void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev);
+void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
+#else
+static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}
+static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
#endif /* CONFIG_USB_PCI */
#endif /* __LINUX_USB_PCI_QUIRKS_H */
@@ -841,7 +841,7 @@ static int uhci_count_ports(struct usb_hcd *hcd)
static const char hcd_name[] = "uhci_hcd";
-#ifdef CONFIG_USB_PCI
+#if defined(CONFIG_USB_PCI) && defined(CONFIG_HAS_IOPORT)
#include "uhci-pci.c"
#define PCI_DRIVER uhci_pci_driver
#endif
@@ -586,12 +586,14 @@ static inline int uhci_aspeed_reg(unsigned int reg)
static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
{
+#ifdef CONFIG_HAS_IOPORT
if (uhci_has_pci_registers(uhci))
return inl(uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+#endif
+ if (uhci_is_aspeed(uhci))
return readl(uhci->regs + uhci_aspeed_reg(reg));
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci))
return readl_be(uhci->regs + reg);
#endif
else
@@ -600,72 +602,97 @@ static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
{
- if (uhci_has_pci_registers(uhci))
+#ifdef CONFIG_HAS_IOPORT
+ if (uhci_has_pci_registers(uhci)) {
outl(val, uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+ return;
+ }
+#endif
+ if (uhci_is_aspeed(uhci)) {
writel(val, uhci->regs + uhci_aspeed_reg(reg));
+ return;
+ }
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci)) {
writel_be(val, uhci->regs + reg);
+ return;
+ }
#endif
- else
- writel(val, uhci->regs + reg);
+ writel(val, uhci->regs + reg);
}
static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
{
+#ifdef CONFIG_HAS_IOPORT
if (uhci_has_pci_registers(uhci))
return inw(uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+#endif
+ if (uhci_is_aspeed(uhci))
return readl(uhci->regs + uhci_aspeed_reg(reg));
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci))
return readw_be(uhci->regs + reg);
#endif
- else
- return readw(uhci->regs + reg);
+ return readw(uhci->regs + reg);
}
static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
{
- if (uhci_has_pci_registers(uhci))
+#ifdef CONFIG_HAS_IOPORT
+ if (uhci_has_pci_registers(uhci)) {
outw(val, uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+ return;
+ }
+#endif
+ if (uhci_is_aspeed(uhci)) {
writel(val, uhci->regs + uhci_aspeed_reg(reg));
+ return;
+ }
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci)) {
writew_be(val, uhci->regs + reg);
+ return;
+ }
#endif
- else
- writew(val, uhci->regs + reg);
+
+ writew(val, uhci->regs + reg);
}
static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
{
+#ifdef CONFIG_HAS_IOPORT
if (uhci_has_pci_registers(uhci))
return inb(uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+#endif
+ if (uhci_is_aspeed(uhci))
return readl(uhci->regs + uhci_aspeed_reg(reg));
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci))
return readb_be(uhci->regs + reg);
#endif
- else
- return readb(uhci->regs + reg);
+
+ return readb(uhci->regs + reg);
}
static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
{
- if (uhci_has_pci_registers(uhci))
+#ifdef CONFIG_HAS_IOPORT
+ if (uhci_has_pci_registers(uhci)) {
outb(val, uhci->io_addr + reg);
- else if (uhci_is_aspeed(uhci))
+ return;
+ }
+#endif
+ if (uhci_is_aspeed(uhci)) {
writel(val, uhci->regs + uhci_aspeed_reg(reg));
+ return;
+ }
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
- else if (uhci_big_endian_mmio(uhci))
+ if (uhci_big_endian_mmio(uhci)) {
writeb_be(val, uhci->regs + reg);
+ return;
+ }
#endif
- else
- writeb(val, uhci->regs + reg);
+ writeb(val, uhci->regs + reg);
}
#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */