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[v2,04/11] riscv: dts: microchip: mpfs: Fix PLIC node

Message ID 69c25dac1243e33bf5a5a893bd6895320d4c87c5.1639660956.git.geert@linux-m68k.org
State Superseded
Headers show
Series [v2,01/11] riscv: dts: canaan: Fix SPI FLASH node names | expand

Commit Message

Geert Uytterhoeven Dec. 16, 2021, 1:37 p.m. UTC 
Fix the device node for the Platform-Level Interrupt Controller (PLIC):
  - Add missing "#address-cells" property,
  - Sort properties according to DT bindings.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v2:
  - Add Reviewed-by.
---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 794da883acb19256..ee59751544a0d3bc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -168,16 +168,17 @@  &cpu3_intc 3 &cpu3_intc 7
 		};
 
 		plic: interrupt-controller@c000000 {
-			#interrupt-cells = <1>;
 			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-			riscv,ndev = <186>;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
 			interrupt-controller;
 			interrupts-extended = <&cpu0_intc 11
 					&cpu1_intc 11 &cpu1_intc 9
 					&cpu2_intc 11 &cpu2_intc 9
 					&cpu3_intc 11 &cpu3_intc 9
 					&cpu4_intc 11 &cpu4_intc 9>;
+			riscv,ndev = <186>;
 		};
 
 		dma@3000000 {