@@ -106,6 +106,7 @@ DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64)
DEF_HELPER_2(fsqrt, f64, env, f64)
+DEF_HELPER_2(fsqrts, f64, env, f64)
DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
@@ -775,6 +775,18 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg)
return ret;
}
+/* fsqrts - fsqrts. */
+float64 helper_fsqrts(CPUPPCState *env, float64 arg)
+{
+ float64 ret = float64r32_sqrt(arg, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_sqrt(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
/* fre - fre. */
float64 helper_fre(CPUPPCState *env, float64 arg)
{
@@ -270,8 +270,7 @@ static void gen_fsqrts(DisasContext *ctx)
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode));
- gen_helper_fsqrt(t1, cpu_env, t0);
- gen_helper_frsp(t1, cpu_env, t1);
+ gen_helper_fsqrts(t1, cpu_env, t0);
set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {