| Message ID | 20211207123539.17346-1-sumeet.r.pawnikar@intel.com |
|---|---|
| State | Accepted |
| Commit | f872f73601b92c86f3da8bdf3e19abd0f1780eb9 |
| Headers | show |
| Series | thermal/drivers/int340x: fix: update VCoRefLow MMIO bit offset for read | expand |
diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c index b25b54d4bac1..e693ec8234fb 100644 --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c @@ -29,7 +29,7 @@ static const char * const fivr_strings[] = { }; static const struct mmio_reg tgl_fivr_mmio_regs[] = { - { 0, 0x5A18, 3, 0x7, 12}, /* vco_ref_code_lo */ + { 0, 0x5A18, 3, 0x7, 11}, /* vco_ref_code_lo */ { 0, 0x5A18, 8, 0xFF, 16}, /* vco_ref_code_hi */ { 0, 0x5A08, 8, 0xFF, 0}, /* spread_spectrum_pct */ { 0, 0x5A08, 1, 0x1, 8}, /* spread_spectrum_clk_enable */
As part of RFIM validation, found that the register definition VCoRefLow of the CPU FIVR registers are different. Current implementation reads it from MMIO offset 0x5A18 and bit offset [12:14]. But the actual correct register definition is from bit offset [11:13]. Updated to the correct bit offset. Fixes: 473be51142ad ("thermal: int340x: processor_thermal: Add RFIM driver") Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Cc: stable@vger.kernel.org # 5.14+ --- drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)