| Message ID | 20211116095042.335224-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [for-6.2] meson.build: Merge riscv32 and riscv64 cpu family | expand |
On 11/16/21 10:50, Richard Henderson wrote: > In ba0e73336200, we merged riscv32 and riscv64 in configure. > However, meson does not treat them the same. We need to merge > them here as well. > > Fixes: ba0e73336200 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > > At the moment, configure for riscv64 host fails during meson. > > > r~ > > --- > meson.build | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Tue, 16 Nov 2021 at 09:52, Richard Henderson <richard.henderson@linaro.org> wrote: > > In ba0e73336200, we merged riscv32 and riscv64 in configure. > However, meson does not treat them the same. We need to merge > them here as well. > > Fixes: ba0e73336200 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > > At the moment, configure for riscv64 host fails during meson. > > > r~ > > --- > meson.build | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/meson.build b/meson.build > index 2ece4fe088..ccc6cefc25 100644 > --- a/meson.build > +++ b/meson.build > @@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', > 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] > > cpu = host_machine.cpu_family() > + > +# Unify riscv* to a single family. > +if cpu in ['riscv32', 'riscv64'] > + cpu = 'riscv' > +endif Needing to do this seems kinda awkward :-( -- PMM
On 11/16/21 11:53 AM, Peter Maydell wrote: >> cpu = host_machine.cpu_family() >> + >> +# Unify riscv* to a single family. >> +if cpu in ['riscv32', 'riscv64'] >> + cpu = 'riscv' >> +endif > > Needing to do this seems kinda awkward :-( Yeah, well. It's either once here, or multiple times later. Or, we admit that riscv32 will never be supported as a host and rename all of our other bits (tcg/riscv and */host/riscv/) to riscv64. r~
On Tue, Nov 16, 2021 at 7:51 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > In ba0e73336200, we merged riscv32 and riscv64 in configure. > However, meson does not treat them the same. We need to merge > them here as well. > > Fixes: ba0e73336200 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > At the moment, configure for riscv64 host fails during meson. > > > r~ > > --- > meson.build | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/meson.build b/meson.build > index 2ece4fe088..ccc6cefc25 100644 > --- a/meson.build > +++ b/meson.build > @@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', > 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] > > cpu = host_machine.cpu_family() > + > +# Unify riscv* to a single family. > +if cpu in ['riscv32', 'riscv64'] > + cpu = 'riscv' > +endif > + > targetos = host_machine.system() > > if cpu in ['x86', 'x86_64'] > -- > 2.25.1 > >
On Tue, Nov 16, 2021 at 7:51 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > In ba0e73336200, we merged riscv32 and riscv64 in configure. > However, meson does not treat them the same. We need to merge > them here as well. > > Fixes: ba0e73336200 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > At the moment, configure for riscv64 host fails during meson. > > > r~ > > --- > meson.build | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/meson.build b/meson.build > index 2ece4fe088..ccc6cefc25 100644 > --- a/meson.build > +++ b/meson.build > @@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', > 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] > > cpu = host_machine.cpu_family() > + > +# Unify riscv* to a single family. > +if cpu in ['riscv32', 'riscv64'] > + cpu = 'riscv' > +endif > + > targetos = host_machine.system() > > if cpu in ['x86', 'x86_64'] > -- > 2.25.1 > >
diff --git a/meson.build b/meson.build index 2ece4fe088..ccc6cefc25 100644 --- a/meson.build +++ b/meson.build @@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() + +# Unify riscv* to a single family. +if cpu in ['riscv32', 'riscv64'] + cpu = 'riscv' +endif + targetos = host_machine.system() if cpu in ['x86', 'x86_64']
In ba0e73336200, we merged riscv32 and riscv64 in configure. However, meson does not treat them the same. We need to merge them here as well. Fixes: ba0e73336200 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- At the moment, configure for riscv64 host fails during meson. r~ --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+)