arm64: dts: ti: k3-j7200: Fix the L2 cache sets

A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

On 12/11/21 10:36PM, Nishanth Menon wrote:
> A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
                                        ^^^

Same as previous patch, do you mean A72? J7200 does not have an A53 core 
and this cache node is for A72 cores anyway.

With this fixed,

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

> 64 bytes and 16-way set-associative cache structure.
> 
> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
> [2] https://www.ti.com/lit/pdf/spruiu1
> 
> Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
> Reported-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> index 958587d3a33d..64fef4e67d76 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -86,7 +86,7 @@ L2_0: l2-cache0 {
>  		cache-level = <2>;
>  		cache-size = <0x100000>;
>  		cache-line-size = <64>;
> -		cache-sets = <2048>;
> +		cache-sets = <1024>;
>  		next-level-cache = <&msmc_l3>;
>  	};
>

Hi Nishanth Menon,
 
On Fri, 12 Nov 2021 22:36:38 -0600, Nishanth Menon wrote:
> A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
> 64 bytes and 16-way set-associative cache structure.
> 

Replaced A53 referenc with A72 locally and applied.

> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [...]
 
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
 
[1/1] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
      commit: d0c826106f3fc11ff97285102b576b65576654ae
 
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
 
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh