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[PULL,09/33] target/riscv: Create RISCVMXL enumeration

Message ID 20211022133812.3972903-10-alistair.francis@opensource.wdc.com
State New
Headers show
Series None | expand

Commit Message

Alistair Francis Oct. 22, 2021, 1:37 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


Move the MXL_RV* defines to enumerators.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---
 target/riscv/cpu_bits.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
2.31.1
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Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 3aa2512d13..cffcd3a5df 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@ 
 #define MISA32_MXL          0xC0000000
 #define MISA64_MXL          0xC000000000000000ULL
 
-#define MXL_RV32            1
-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;
 
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001