| Message ID | 1438005139-16562-1-git-send-email-srinivas.kandagatla@linaro.org |
|---|---|
| State | Accepted |
| Commit | 504155cafffbe35d5678c10af7777303ead01928 |
| Headers | show
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[78.147.3.201]) by smtp.gmail.com with ESMTPSA id r8sm13791670wiz.5.2015.07.27.06.52.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Jul 2015 06:52:24 -0700 (PDT) From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> To: agross@codeaurora.org, linux-arm-msm@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Russell King <linux@arm.linux.org.uk>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Subject: [PATCH v1 7/7] ARM: dts: apq8064: fix missing gsbi cell-index Date: Mon, 27 Jul 2015 14:52:19 +0100 Message-Id: <1438005139-16562-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438004945-16175-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1438004945-16175-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: <patchwork-forward.linaro.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. 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diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b7c282b..d2e94d6 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -249,6 +249,7 @@ gsbi3: gsbi@16200000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; reg = <0x16200000 0x100>; clocks = <&gcc GSBI3_H_CLK>; clock-names = "iface";
Without this i2c instance for missing cell-index nodes would fail, fix it by adding correct cell-index. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + 1 file changed, 1 insertion(+)