| Message ID | 20210910184147.336618-10-paul.kocialkowski@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | [01/22] clk: sunxi-ng: v3s: Make the ISP PLL clock public | expand |
On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > controller. The controller uses a separate D-PHY, which is the same > that is otherwise used for MIPI DSI, but used in Rx mode. > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > not have access to any parallel interface pins. > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > support the MIPI CSI-2 interface. > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > even when no sensor is connected. This will result in a probe failure > for the controller as long as no sensor is connected but this is fine > since no other interface is available. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > --- > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index a77b63362a1d..ec7fa6459547 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > #size-cells = <0>; > }; > > + csi0: camera@1cb0000 { > + compatible = "allwinner,sun8i-v3s-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + assigned-clocks = <&ccu CLK_CSI1_SCLK>; > + assigned-clock-parents = <&ccu CLK_PLL_ISP>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csi0_in_mipi_csi2: endpoint { > + remote-endpoint = <&mipi_csi2_out_csi0>; > + }; > + }; > + }; > + }; > + > csi1: camera@1cb4000 { > compatible = "allwinner,sun8i-v3s-csi"; > reg = <0x01cb4000 0x3000>; All of the new nodes should be added above this one, to maintain unit address order. Regards, Samuel > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > #interrupt-cells = <3>; > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > }; > + > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > + "allwinner,sun6i-a31-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + phys = <&dphy>; > + phy-names = "dphy"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + > + mipi_csi2_out_csi0: endpoint { > + remote-endpoint = <&csi0_in_mipi_csi2>; > + }; > + }; > + }; > + }; > + > + dphy: d-phy@1cb2000 { > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > + reg = <0x01cb2000 0x1000>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_MIPI_CSI>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + allwinner,direction = "rx"; > + status = "disabled"; > + #phy-cells = <0>; > + }; > }; > }; >
Hi Samuel, On Fri 10 Sep 21, 21:32, Samuel Holland wrote: > On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > > controller. The controller uses a separate D-PHY, which is the same > > that is otherwise used for MIPI DSI, but used in Rx mode. > > > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > > not have access to any parallel interface pins. > > > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > > support the MIPI CSI-2 interface. > > > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > > even when no sensor is connected. This will result in a probe failure > > for the controller as long as no sensor is connected but this is fine > > since no other interface is available. > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > --- > > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > > 1 file changed, 72 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > > index a77b63362a1d..ec7fa6459547 100644 > > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > > #size-cells = <0>; > > }; > > > > + csi0: camera@1cb0000 { > > + compatible = "allwinner,sun8i-v3s-csi"; > > + reg = <0x01cb0000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>, > > + <&ccu CLK_DRAM_CSI>; > > + clock-names = "bus", "mod", "ram"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + assigned-clocks = <&ccu CLK_CSI1_SCLK>; > > + assigned-clock-parents = <&ccu CLK_PLL_ISP>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@1 { > > + reg = <1>; > > + > > + csi0_in_mipi_csi2: endpoint { > > + remote-endpoint = <&mipi_csi2_out_csi0>; > > + }; > > + }; > > + }; > > + }; > > + > > csi1: camera@1cb4000 { > > compatible = "allwinner,sun8i-v3s-csi"; > > reg = <0x01cb4000 0x3000>; > > All of the new nodes should be added above this one, to maintain unit > address order. Good catch, this was an overlook on my side. Thanks, Paul > Regards, > Samuel > > > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > > #interrupt-cells = <3>; > > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > + > > + mipi_csi2: csi@1cb1000 { > > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > > + "allwinner,sun6i-a31-mipi-csi2"; > > + reg = <0x01cb1000 0x1000>; > > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>; > > + clock-names = "bus", "mod"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + phys = <&dphy>; > > + phy-names = "dphy"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg = <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg = <1>; > > + > > + mipi_csi2_out_csi0: endpoint { > > + remote-endpoint = <&csi0_in_mipi_csi2>; > > + }; > > + }; > > + }; > > + }; > > + > > + dphy: d-phy@1cb2000 { > > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > > + reg = <0x01cb2000 0x1000>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_MIPI_CSI>; > > + clock-names = "bus", "mod"; > > + resets = <&ccu RST_BUS_CSI>; > > + allwinner,direction = "rx"; > > + status = "disabled"; > > + #phy-cells = <0>; > > + }; > > }; > > }; > > > -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a77b63362a1d..ec7fa6459547 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -612,6 +612,34 @@ spi0: spi@1c68000 { #size-cells = <0>; }; + csi0: camera@1cb0000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + assigned-clocks = <&ccu CLK_CSI1_SCLK>; + assigned-clock-parents = <&ccu CLK_PLL_ISP>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi0_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi0>; + }; + }; + }; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-v3s-mipi-csi2", + "allwinner,sun6i-a31-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + phys = <&dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi0: endpoint { + remote-endpoint = <&csi0_in_mipi_csi2>; + }; + }; + }; + }; + + dphy: d-phy@1cb2000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01cb2000 0x1000>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_MIPI_CSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + allwinner,direction = "rx"; + status = "disabled"; + #phy-cells = <0>; + }; }; };
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel interface pins. Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to support the MIPI CSI-2 interface. Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 even when no sensor is connected. This will result in a probe failure for the controller as long as no sensor is connected but this is fine since no other interface is available. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+)