| Message ID | 20210910184147.336618-14-paul.kocialkowski@bootlin.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [01/22] clk: sunxi-ng: v3s: Make the ISP PLL clock public | expand |
Hi, On Sat, Sep 11, 2021 at 2:42 AM Paul Kocialkowski <paul.kocialkowski@bootlin.com> wrote: > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > covers both the protocol and D-PHY. It can be connected to the CSI > interface as a V4L2 subdev through the fwnode graph. > > This is not done by default since connecting the bridge without a > subdev attached to it will cause a failure on the CSI driver. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> I believe you tagged the wrong patch to not be merged? AFAICT it should be the next patch that hooks up OV8865, not this one. > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > index ac97eac91349..1fa51f7ef063 100644 > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > status = "disabled"; > }; > > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_MIPI_CSI>, > + <&ccu CLK_CSI_MISC>; > + clock-names = "bus", "mod", "mipi", "misc"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > hdmi: hdmi@1ee0000 { > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > reg = <0x01ee0000 0x10000>; > -- > 2.32.0 > >
Hi Chen-Yu, On Sat 11 Sep 21, 10:53, Chen-Yu Tsai wrote: > Hi, > > On Sat, Sep 11, 2021 at 2:42 AM Paul Kocialkowski > <paul.kocialkowski@bootlin.com> wrote: > > > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > > covers both the protocol and D-PHY. It can be connected to the CSI > > interface as a V4L2 subdev through the fwnode graph. > > > > This is not done by default since connecting the bridge without a > > subdev attached to it will cause a failure on the CSI driver. > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > I believe you tagged the wrong patch to not be merged? AFAICT it > should be the next patch that hooks up OV8865, not this one. Yes you are definitely right, this patch is good for merge and the next one is not. Thanks, Paul > > --- > > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > > index ac97eac91349..1fa51f7ef063 100644 > > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > > status = "disabled"; > > }; > > > > + mipi_csi2: csi@1cb1000 { > > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > > + reg = <0x01cb1000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI_SCLK>, > > + <&ccu CLK_MIPI_CSI>, > > + <&ccu CLK_CSI_MISC>; > > + clock-names = "bus", "mod", "mipi", "misc"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg = <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > hdmi: hdmi@1ee0000 { > > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > > reg = <0x01ee0000 0x10000>; > > -- > > 2.32.0 > > > > -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index ac97eac91349..1fa51f7ef063 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { status = "disabled"; }; + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>;
MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It can be connected to the CSI interface as a V4L2 subdev through the fwnode graph. This is not done by default since connecting the bridge without a subdev attached to it will cause a failure on the CSI driver. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)