@@ -70,4 +70,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
new file mode 100644
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+/dts-v1/;
+
+#include "s32g2.dtsi"
+
+/ {
+ model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
+ compatible = "nxp,s32g274a-evb", "nxp,s32g2";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* UART (J58) to Micro USB port */
+&uart0 {
+ status = "okay";
+};
new file mode 100644
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+/dts-v1/;
+
+#include "s32g2.dtsi"
+
+/ {
+ model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
+ compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* UART (J2) to Micro USB port */
+&uart0 {
+ status = "okay";
+};
+
+/* UART (J1) to Micro USB port */
+&uart1 {
+ status = "okay";
+};
Add initial device-trees of NXP S32G2's Evaluation Board (S32G-VNP-EVB) and Reference Design 2 Board (S32G-VNP-RDB2). Signed-off-by: Chester Lin <clin@suse.com> --- Changes in v2: - Correct the model string. - Rename the compatible vendor string to "nxp,". - Move the serial/uart aliases from the SoC .dtsi to board .dts files. - Add comments for the uart markings on PCB. arch/arm64/boot/dts/freescale/Makefile | 2 ++ .../arm64/boot/dts/freescale/s32g274a-evb.dts | 26 +++++++++++++++ .../boot/dts/freescale/s32g274a-rdb2.dts | 32 +++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts