Message ID | 20210822193145.1312668-6-alvin@pqrs.dk |
---|---|
State | New |
Headers | show |
Series | net: dsa: add support for RTL8365MB-VC | expand |
On 8/22/2021 9:31 PM, Alvin Šipraga wrote: > From: Alvin Šipraga <alsi@bang-olufsen.dk> > > The RTL8365MB-VC ethernet switch controller has 4 internal PHYs for its > user-facing ports. All that is needed is to let the PHY driver core > pick up the IRQ made available by the switch driver. > > Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
On Sun, Aug 22, 2021 at 9:32 PM Alvin Šipraga <alvin@pqrs.dk> wrote: > From: Alvin Šipraga <alsi@bang-olufsen.dk> > > The RTL8365MB-VC ethernet switch controller has 4 internal PHYs for its > user-facing ports. All that is needed is to let the PHY driver core > pick up the IRQ made available by the switch driver. > > Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 11be60333fa8..a5671ab896b3 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -1023,6 +1023,14 @@ static struct phy_driver realtek_drvs[] = { .resume = genphy_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, + }, { + PHY_ID_MATCH_EXACT(0x001cc942), + .name = "RTL8365MB-VC Gigabit Ethernet", + /* Interrupt handling analogous to RTL8366RB */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .suspend = genphy_suspend, + .resume = genphy_resume, }, };