| Message ID | 1629272675-7142-1-git-send-email-haibo.chen@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: imx8qm: minor fix for schema dts check | expand |
On Wed, Aug 18, 2021 at 03:44:35PM +0800, haibo.chen@nxp.com wrote: > From: Haibo Chen <haibo.chen@nxp.com> > > Add minor fix to pass schema dts check. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > --- > .../arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 18 +++++++++--------- > .../boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++-- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > index a79f42a9618e..639220dbff00 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > @@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b010000 0x10000>; > clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, > - <&sdhc0_lpcg IMX_LPCG_CLK_5>, > - <&sdhc0_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc0_lpcg IMX_LPCG_CLK_0>, > + <&sdhc0_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_0>; > status = "disabled"; > }; > @@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b020000 0x10000>; > clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, > - <&sdhc1_lpcg IMX_LPCG_CLK_5>, > - <&sdhc1_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc1_lpcg IMX_LPCG_CLK_0>, > + <&sdhc1_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_1>; > fsl,tuning-start-tap = <20>; > fsl,tuning-step= <2>; > @@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b030000 0x10000>; > clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, > - <&sdhc2_lpcg IMX_LPCG_CLK_5>, > - <&sdhc2_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc2_lpcg IMX_LPCG_CLK_0>, > + <&sdhc2_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_2>; > status = "disabled"; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > index 42637a45701c..17bbe2e16126 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > @@ -13,9 +13,9 @@ > }; > > &usdhc1 { > - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; We should document "fsl,imx8qm-usdhc" instead? Shawn > }; > > &usdhc2 { > - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > }; > -- > 2.17.1 >
On Wed, Aug 18, 2021 at 03:44:35PM +0800, haibo.chen@nxp.com wrote: > From: Haibo Chen <haibo.chen@nxp.com> > > Add minor fix to pass schema dts check. Please have separate patch for clock and compatible changes. Also provide schema check warning/error messages in commit log. Shawn > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > --- > .../arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 18 +++++++++--------- > .../boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++-- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > index a79f42a9618e..639220dbff00 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi > @@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b010000 0x10000>; > clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, > - <&sdhc0_lpcg IMX_LPCG_CLK_5>, > - <&sdhc0_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc0_lpcg IMX_LPCG_CLK_0>, > + <&sdhc0_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_0>; > status = "disabled"; > }; > @@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b020000 0x10000>; > clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, > - <&sdhc1_lpcg IMX_LPCG_CLK_5>, > - <&sdhc1_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc1_lpcg IMX_LPCG_CLK_0>, > + <&sdhc1_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_1>; > fsl,tuning-start-tap = <20>; > fsl,tuning-step= <2>; > @@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 { > interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b030000 0x10000>; > clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, > - <&sdhc2_lpcg IMX_LPCG_CLK_5>, > - <&sdhc2_lpcg IMX_LPCG_CLK_0>; > - clock-names = "ipg", "per", "ahb"; > + <&sdhc2_lpcg IMX_LPCG_CLK_0>, > + <&sdhc2_lpcg IMX_LPCG_CLK_5>; > + clock-names = "ipg", "ahb", "per"; > power-domains = <&pd IMX_SC_R_SDHC_2>; > status = "disabled"; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > index 42637a45701c..17bbe2e16126 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > @@ -13,9 +13,9 @@ > }; > > &usdhc1 { > - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > }; > > &usdhc2 { > - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > }; > -- > 2.17.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index a79f42a9618e..639220dbff00 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, - <&sdhc0_lpcg IMX_LPCG_CLK_5>, - <&sdhc0_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "per", "ahb"; + <&sdhc0_lpcg IMX_LPCG_CLK_0>, + <&sdhc0_lpcg IMX_LPCG_CLK_5>; + clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; }; @@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b020000 0x10000>; clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, - <&sdhc1_lpcg IMX_LPCG_CLK_5>, - <&sdhc1_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "per", "ahb"; + <&sdhc1_lpcg IMX_LPCG_CLK_0>, + <&sdhc1_lpcg IMX_LPCG_CLK_5>; + clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; @@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b030000 0x10000>; clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, - <&sdhc2_lpcg IMX_LPCG_CLK_5>, - <&sdhc2_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "per", "ahb"; + <&sdhc2_lpcg IMX_LPCG_CLK_0>, + <&sdhc2_lpcg IMX_LPCG_CLK_5>; + clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi index 42637a45701c..17bbe2e16126 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -13,9 +13,9 @@ }; &usdhc1 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; &usdhc2 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; };