diff mbox series

[WIP] arm64: dts: broadcom: bcm4908: Add PCIe controllers

Message ID 20210819155408.25770-1-zajec5@gmail.com
State New
Headers show
Series [WIP] arm64: dts: broadcom: bcm4908: Add PCIe controllers | expand

Commit Message

Rafał Miłecki Aug. 19, 2021, 3:54 p.m. UTC 
From: Rafał Miłecki <rafal@milecki.pl>

BCM4908 SoC has 3 PCIe controllers. Describe them.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
This is WIP. It's enough to initialize PCIe controllers and detect
attached devices. Checking DTS files however results in complains about
missing "dma-ranges", interrupt mapping & "msi-controller".
---
 .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 53 ++++++++++++++++++-
 1 file changed, 52 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
index 984c737fa627..f09611697863 100644
--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
@@ -267,6 +267,57 @@  pmb: power-controller@2800c0 {
 		};
 	};
 
+	pcie@80040000 {
+		compatible = "brcm,bcm4908-pcie";
+		reg = <0x0 0x80040000 0x0 0xa000>;
+		power-domains = <&pmb BCM_PMB_PCIE0>;
+		resets = <&pcie_reset 0>;
+		reset-names = "perst";
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie";
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		// BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+		ranges = <0x02000000 0x0 0xc0000000  0x0 0xc0000000  0x0 0x10000000>;
+	};
+
+	pcie@80050000 {
+		compatible = "brcm,bcm4908-pcie";
+		reg = <0x0 0x80050000 0x0 0xa000>;
+		power-domains = <&pmb BCM_PMB_PCIE1>;
+		resets = <&pcie_reset 1>;
+		reset-names = "perst";
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie";
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		// BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+		ranges = <0x02000000 0x0 0xd0000000  0x0 0xd0000000  0x0 0x10000000>;
+	};
+
+	pcie@80060000 {
+		compatible = "brcm,bcm4908-pcie";
+		reg = <0x0 0x80060000 0x0 0xa000>;
+		power-domains = <&pmb BCM_PMB_PCIE2>;
+		resets = <&pcie_reset 2>;
+		reset-names = "perst";
+		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie";
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		// BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+		ranges = <0x02000000 0x0 0xe0000000  0x0 0xe0000000  0x0 0x10000000>;
+	};
+
 	bus@ff800000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -320,7 +371,7 @@  misc@2600 {
 			#size-cells = <1>;
 			ranges = <0x00 0x2600 0xe4>;
 
-			reset-controller@2644 {
+			pcie_reset: reset-controller@2644 {
 				compatible = "brcm,bcm4908-misc-pcie-reset";
 				reg = <0x44 0x04>;
 				#reset-cells = <1>;