| Message ID | 1628754078-29779-2-git-send-email-rajpat@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand |
On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote: > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QSPI DT node and qspi_opp_table for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 53a21d0..f8dd5ff 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -415,6 +415,25 @@ > method = "smc"; > }; > > + qspi_opp_table: qspi-opp-table { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-150000000 { > + opp-hz = /bits/ 64 <150000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > +
On 2021-08-12 18:39, Matthias Kaehlcke wrote: > On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote: >> From: Roja Rani Yarubandi <rojay@codeaurora.org> >> >> Add QSPI DT node and qspi_opp_table for SC7280 SoC. >> >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> >> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 >> ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 53a21d0..f8dd5ff 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -415,6 +415,25 @@ >> method = "smc"; >> }; >> >> + qspi_opp_table: qspi-opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-75000000 { >> + opp-hz = /bits/ 64 <75000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-150000000 { >> + opp-hz = /bits/ 64 <150000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-300000000 { >> + opp-hz = /bits/ 64 <300000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + > > From v3: > > roja> Can we move this "qspi_opp_table" to / from /soc? > > bjorn> If you have made a proper attempt to convince Rob and Mark that > bjorn> a child "opp-table" in a SPI master is not a SPI device - and > the > bjorn> conclusion is that this is not a good idea...then yes it should > live > bjorn> outside /soc. > > I didn't see a follow up on this, was such an attempt made? Is there a > link to the discussion? For now I am keeping qspi_opp_table and qup_opp_table outside the SoC and posting V6. I will continue the discussion with DT folks and once concluded I will update as required.
On Thu, Aug 26, 2021 at 06:29:41PM +0530, rajpat@codeaurora.org wrote: > On 2021-08-12 18:39, Matthias Kaehlcke wrote: > > On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote: > > > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > > > > > Add QSPI DT node and qspi_opp_table for SC7280 SoC. > > > > > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > > > --- > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 > > > ++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 62 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > index 53a21d0..f8dd5ff 100644 > > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > @@ -415,6 +415,25 @@ > > > method = "smc"; > > > }; > > > > > > + qspi_opp_table: qspi-opp-table { > > > + compatible = "operating-points-v2"; > > > + > > > + opp-75000000 { > > > + opp-hz = /bits/ 64 <75000000>; > > > + required-opps = <&rpmhpd_opp_low_svs>; > > > + }; > > > + > > > + opp-150000000 { > > > + opp-hz = /bits/ 64 <150000000>; > > > + required-opps = <&rpmhpd_opp_svs>; > > > + }; > > > + > > > + opp-300000000 { > > > + opp-hz = /bits/ 64 <300000000>; > > > + required-opps = <&rpmhpd_opp_nom>; > > > + }; > > > + }; > > > + > > > > From v3: > > > > roja> Can we move this "qspi_opp_table" to / from /soc? > > > > bjorn> If you have made a proper attempt to convince Rob and Mark that > > bjorn> a child "opp-table" in a SPI master is not a SPI device - and the > > bjorn> conclusion is that this is not a good idea...then yes it should > > live > > bjorn> outside /soc. > > > > I didn't see a follow up on this, was such an attempt made? Is there a > > link to the discussion? > > For now I am keeping qspi_opp_table and qup_opp_table outside the SoC and > posting V6. > I will continue the discussion with DT folks and once concluded I will > update as required. Do you have a link to that discussion so that people can follow along or chime in?
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d0..f8dd5ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -415,6 +415,25 @@ method = "smc"; }; + qspi_opp_table: qspi-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1318,6 +1337,24 @@ }; }; + qspi: spi@88dc000 { + compatible = "qcom,qspi-v1"; + reg = <0 0x088dc000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", "core"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &cnoc2 SLAVE_QSPI_0 0>; + interconnect-names = "qspi-config"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qspi_opp_table>; + status = "disabled"; + + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; @@ -1513,6 +1550,31 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + qspi_clk: qspi-clk { + pins = "gpio14"; + function = "qspi_clk"; + }; + + qspi_cs0: qspi-cs0 { + pins = "gpio15"; + function = "qspi_cs"; + }; + + qspi_cs1: qspi-cs1 { + pins = "gpio19"; + function = "qspi_cs"; + }; + + qspi_data01: qspi-data01 { + pins = "gpio12", "gpio13"; + function = "qspi_data"; + }; + + qspi_data12: qspi-data12 { + pins = "gpio16", "gpio17"; + function = "qspi_data"; + }; + qup_uart5_default: qup-uart5-default { pins = "gpio46", "gpio47"; function = "qup13";