diff mbox

[v2,1/2] target-arm/kvm64: Add cortex-a53 cpu support

Message ID 1433207452-4512-2-git-send-email-shannon.zhao@linaro.org
State New
Headers show

Commit Message

Shannon Zhao June 2, 2015, 1:10 a.m. UTC 
From: Shannon Zhao <shannon.zhao@linaro.org>

Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
added Cortex-A53 cpu support for target-arm, this patch just enables it
for kvm-arm.

Here adding XGENE_POTENZA just makes the enum continuous.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 target-arm/cpu64.c      | 1 +
 target-arm/kvm-consts.h | 4 ++++
 target-arm/kvm64.c      | 2 ++
 3 files changed, 7 insertions(+)

Comments

Peter Maydell June 12, 2015, 2:17 p.m. UTC | #1 
On 2 June 2015 at 02:10,  <shannon.zhao@linaro.org> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
> added Cortex-A53 cpu support for target-arm, this patch just enables it
> for kvm-arm.
>
> Here adding XGENE_POTENZA just makes the enum continuous.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---

> --- a/target-arm/kvm64.c
> +++ b/target-arm/kvm64.c
> @@ -50,6 +50,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
>          KVM_ARM_TARGET_AEM_V8,
>          KVM_ARM_TARGET_FOUNDATION_V8,
>          KVM_ARM_TARGET_CORTEX_A57,
> +        KVM_ARM_TARGET_XGENE_POTENZA,
> +        KVM_ARM_TARGET_CORTEX_A53,
>          QEMU_KVM_ARM_TARGET_NONE
>      };
>      struct kvm_vcpu_init init;

This is wrong -- this list should only include CPUs which were supported
in the very old kernels which don't know about PREFERRED_TARGET (see
the comment above the array).

Since the patchset looks OK otherwise, I'll just delete those two
lines and put it into target-arm.next.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index bf7dd68..dd6f9d8 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -159,6 +159,7 @@  static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
     cpu->midr = 0x410fd034;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h
index aea12f1..943bf89 100644
--- a/target-arm/kvm-consts.h
+++ b/target-arm/kvm-consts.h
@@ -127,6 +127,8 @@  MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
 #define QEMU_KVM_ARM_TARGET_AEM_V8 0
 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
+#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
+#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
 
 /* There's no kernel define for this: sentinel value which
  * matches no KVM target value for either 64 or 32 bit
@@ -137,6 +139,8 @@  MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53)
 #else
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7)
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 93c1ca8..cd84132 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -50,6 +50,8 @@  bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
         KVM_ARM_TARGET_AEM_V8,
         KVM_ARM_TARGET_FOUNDATION_V8,
         KVM_ARM_TARGET_CORTEX_A57,
+        KVM_ARM_TARGET_XGENE_POTENZA,
+        KVM_ARM_TARGET_CORTEX_A53,
         QEMU_KVM_ARM_TARGET_NONE
     };
     struct kvm_vcpu_init init;