| Message ID | 1432972448-10332-3-git-send-email-daniel.thompson@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30/05/15 10:21, Maxime Coquelin wrote: > HI Daniel, > > On 05/30/2015 09:54 AM, Daniel Thompson wrote: >> This adds documentation of device tree bindings for the clock related >> portions of the STM32 RCC block. >> >> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> >> --- >> .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 >> ++++++++++++++++++++++ >> 1 file changed, 65 insertions(+) >> <snip> >> +Example: >> + >> + /* Gated clock, AHB1 bit 0 (GPIOA) */ >> + ... { >> + clocks = <&rcc 0 0> >> + }; >> + >> + /* Gated clock, AHB2 bit 4 (GPIOA) */ > s/GPIOA/CRYP/ Oops! Will fix. >> + ... { >> + clocks = <&rcc 0 36> >> + }; >> + >> +Specifying other clocks >> +======================= >> + >> +The primary index must be set to 1. >> + >> +The secondary index is bound with the following magic numbers: >> + >> + 0 SYSTICK >> + 1 FCLK > How do you plan to handle the SAI & I2S clocks? > By adding index 3? Pretty much. Tentatively I'm thinking of: 2 I2S clocks 3 SAI1_A clock 4 SAI1_B clock 5 LCD-TFT clock Note: Sort order is based on the vertical ordering in the clock tree diagram in the data sheet. Only reason not to include these in the bindings immediately is that I wanted to check how/if these clocks are gated. The clock tree diagram shows them having individual clock gates so before proposing them using magic numbers I wanted to double check if these values can be identified at gates clocks. Daniel.
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..9715d09 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (GPIOA) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + };
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt